tag: signal integrity

GDDR6 And HBM2: Signal Integrity Challenges For AI
By Frank Ferro - 11 Apr, 2019 - Comments: 0

In a nutshell, Artificial Intelligence (AI) and its growing list of applications demand a considerably large amount of bandwidth to push bits in and out of memory at the highest speeds possible. AI has been getting a lot of industry attention, and certainly it’s not a new phenomenon because it’s been gaining even greater traction in the last year or two. This is especially true since a n... » read more

GDDR6: Signal Integrity Challenges For Automotive Systems
By Frank Ferro - 14 Mar, 2019 - Comments: 0

Signal integrity (SI) is at the forefront of SoC and system designers’ thinking as they plan for upcoming high-speed GDDR6 DRAM and PHY implementations for automotive and advanced driver assistance system (ADAS) applications. Rambus and its partners are closely looking at how GDDR6’s 16 gigabit per second speed at each pin affects signal integrity given the cost and system constraints for a... » read more

2.5D, 3D Power Integrity
By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

New Design Approaches At 7/5nm
By Ed Sperling - 04 Mar, 2019 - Comments: 0

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Blog Review: Mar. 14
By Jesse Allen - 14 Mar, 2018 - Comments: 0

Cadence's Meera Collier considers the issues of bias implementation in algorithms and AI systems, and whether immense training sets can really solve the problem. Mentor's Cristian Filip digs into the evolution of signal integrity analysis methods and why different data rates require different solutions. Synopsys' Naveen G explains key features introduced in the latest generation of interc... » read more

GDDR6 PHYs: From The Data Center To Self-Driving Cars
By Frank Ferro - 08 Feb, 2018 - Comments: 0

The demand for ever-increasing bandwidth has resulted in a growing interest in GDDR across a number of market verticals, including data centers and the automotive sector. As an example of the former, deep learning applications require ever-increasing speed and bandwidth memory solutions in the data center. In deep learning and other emerging technologies, GDDR memory can help companies addre... » read more

The Promises And Challenges Of 7nm
By Frank Ferro - 09 Nov, 2017 - Comments: 0

Despite a waning Moore’s Law and the increasing costs of advanced process nodes, the semiconductor industry is steadily approaching 7 nanometers (nm). The demand for 7nm is driving expected initial tape-outs from fabs by the end of 2017, with initial volumes beginning in 2018 and ramping up by 2019. Silicon fabbed on 7nm nodes will offer a number of benefits for chipmakers, including lower po... » read more

Blog Review: Oct. 18
By Jesse Allen - 18 Oct, 2017 - Comments: 0

Mentor's Nitin Bhagwath suggests some ways to deal with undesirable signal integrity effects in DDR designs. Cadence's Ken Willis argues that for multi-gigabit serial link interfaces, signal integrity analysis should start upstream of the traditional post-layout verification step. Synopsys' Ravindra Aneja contends that understanding formal core data can reduce the overall effort and short... » read more

Understanding SerDes Signal Integrity Challenges
By Bill Fuller - 13 Apr, 2017 - Comments: 0

Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

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