tag: Silicon Creations

Analog Consolidation Spurs New Round Of Startups
By Bryon Moyer - 08 Aug, 2024 - Comments: 0

A new wave of startups is rising to meet the growing need for specialized analog customization in chip design projects, opening the door to more affordable custom designs. These startups are breathing new life into a sector, which as a result of consolidation has favored only the largest chipmakers. As larger analog companies acquire smaller ones, many companies that were previously engaged ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Feb, 2022 - Comments: 0

Nvidia's proposed acquisition of Arm is officially off. The deal faced significant pushback from regulatory agencies in the UK, USA, and Europe, which feared it would reduce or limit competition in areas like data center. Nvidia indicated it would continue working with Arm, and it will retain a 20-year Arm license. (SoftBank will retain the $1.25 billion prepaid by Nvidia.) SoftBank said it wil... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Test Chips Play Larger Role At Advanced Nodes
By Ann Mutschler - 27 Jun, 2019 - Comments: 0

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

Wrestling With High-Speed SerDes
By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Why IP Quality Is So Difficult To Determine
By Ann Mutschler - 30 May, 2019 - Comments: 0

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

Frenzy At 10/7nm
By Ann Mutschler - 14 Sep, 2017 - Comments: 1

The number of chipmakers rushing to 10/7nm is rising, despite a slowdown in Moore's Law scaling and the increased difficulty and cost of developing chips at the most advanced nodes. How long this trend continues remains to be seen. It's likely that 7/5nm will require new manufacturing equipment, tools, materials and transistor structures. Beyond that, there is no industry-accepted roadmap, m... » read more

IP Biz Changes As Markets Fragment
By Ed Sperling - 22 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"]' S... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy