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Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

The Week In Review: Design


Tools Mentor Graphics launched the company's third generation data-center friendly emulation platform, Veloce Strato. The emulator has a capacity of 2.5BG when fully loaded, and total capacity can be increased by linking emulators. It has available slots for 64 Advanced Verification Boards (AVBs) and fully loaded consumes up to 50KW (22.7 W/Mgate) of power. Aldec uncorked the latest versi... » read more

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