tag: silicon germanium

Reliability After Planar Silicon
By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

What Will 7nm And 5nm Look Like?
By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

The End Of Silicon?
By Katherine Derbyshire - 04 May, 2015 - Comments: 1

As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem. In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reduci... » read more

Next Channel Materials?
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

An Inside Look At The GlobalFoundries-IBM Deal
By Ed Sperling - 20 Nov, 2014 - Comments: 3

GlobalFoundries' proposed acquisition of IBM Microelectronics is the kind of deal that will have business schools talking for many years to come—a gargantuan combination of expertise and technology, built on the back of high-profile business successes and failures, long-running legal struggles and global politics—with far-reaching implications for all parts of the semiconductor supply chain... » read more

More Problems Ahead
By Ed Sperling - 10 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: Where are the most severe issues these days? Is it on the design... » read more

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