tag: simulation

ON Semiconductor Conquers Verification Challenges
By Mentor, a Siemens Business - 06 Mar, 2019 - Comments: 0

Motor controller IC design for automotive applications, such as power mirror, seats, door locks, and door lift control, creates exceptional verification challenges. Particularly because these ICs must work for over 10 years and they live in harsh environments including -40° C to 150° C temperature ranges, voltages ranging from 7V to 40V, and potential electrostatic discharge and electromagnet... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Week in Review: Design, Low Power
By Susan Rambo - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Designing Networking Chips
By Ed Sperling - 07 Feb, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Can AI, 5G Chips Be Verified?
By Ed Sperling - 31 Jan, 2019 - Comments: 0

AI and 5G bode well for the semiconductor industry. They will require many billions of new, semi-customized and highly complex chips from the edge all the way to the data center, and they will require massive amounts of engineering time and tooling. But these technologies also are raising lots of questions on the design and verification front about what else can be automated and how to do it. ... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Chip Industry In Rapid Transition
By Ed Sperling - 09 Jan, 2019 - Comments: 0

Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation
By Himanshu Bhatt - 13 Dec, 2018 - Comments: 1

By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

The Cost Of Accuracy
By Brian Bailey - 13 Dec, 2018 - Comments: 0

How accurate does a system need to be, and what are you willing to pay for that accuracy? There are many sources of inaccuracy throughout the development flow of electronic systems, most of which involve complex tradeoffs. Inaccuracy leaves an impact on your design in ways you are not even aware of, hidden by best practices or guard-banding. EDA tools also inject some inaccuracy. As the i... » read more

SMART Fracture
By Ansys - 12 Dec, 2018 - Comments: 0

With the new unstructured mesh method (UMM) in ANSYS Mechanical, engineers can reduce preprocessing time by employing UMM’s automatically generated all-tetrahedral (tet) mesh for crack fronts, while achieving the same high-fidelity results as a simulation run with the ideal hex mesh configuration. Meshing time has been reduced from up to several days to a few minutes. Using UMM, ANSYS has ... » read more

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