tag: simulation

Verifying AI, Machine Learning
By Ed Sperling - 28 Sep, 2017 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

Verification’s Breaking Points
By Ann Mutschler - 28 Sep, 2017 - Comments: 2

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. The result is a new level of unpredictability about how much it will cost to complete the verification process, whether it will meet narrow market windows, and whether quality will be traded off to get a chip out on time in the hopes that it c... » read more

How To Make Autonomous Vehicles Reliable
By Ann Mutschler - 11 Sep, 2017 - Comments: 1

The number of unknowns in automotive chips, subsystems and entire vehicles is growing as higher levels of driver assistance are deployed, sparking new concerns and approaches about how to improve reliability of these systems. Advanced Driver Assistance Systems (ADAS) will need to detect objects, animals and people, and they will be used for parking assistance, night vision and collision avoi... » read more

Lam Research Acquires Coventor
By Mark LaPedus - 31 Aug, 2017 - Comments: 0

In a move to expand its product portfolio, Lam Research has acquired Coventor, a provider of simulation and modeling solutions for the semiconductor and MEMS industries. With the acquisition of Coventor, fab tool vendor Lam enters the simulation and modeling technology market. Coventor sells the so-called SEMulator3D modeling and analysis platform, which simulates a fab process flow. The “... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

Frontloading CFD-Required Technologies
By Mentor, a Siemens Business - 23 Aug, 2017 - Comments: 0

Today, manufacturing product design cycles need to get shorter and shorter as either new or increased numbers of products get to the market faster. In the automotive industry for example, with either facelifts to existing car models, or the next generation of the model appearing almost every 3-4 years, and an increasing number of new models appearing on the market, the demand on engineering des... » read more

Machine Learning In The Fab
By Ed Sperling - 17 Aug, 2017 - Comments: 0

Machine learning is exploding, especially where there are massive amounts of data to contend with and lots of potential interactions. This leads to two obvious insertion points in the semiconductor field. One is on the design side, where just getting an advanced design to function is an enormous challenge. That challenge increases as the need for reliability in some market increases. It's d... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

How Much Verification Is Necessary?
By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Hybrid Emulation
By Brian Bailey - 19 Jul, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

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