tag: simulation

Carving Up Verification
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

VCS Fine-Grained Parallelism Simulation Performance Technology
By Synopsys - 22 Mar, 2017 - Comments: 0

Learn how fine-grained parallelism simulation technology enables delivery of breakthrough parallel simulation performance improvement needed to reduce turn-around time for critical-path tests. » read more

Worst-Case Results Causing Problems
By Ed Sperling - 09 Mar, 2017 - Comments: 0

The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to create its own set of issues. This is particularly true at 16/14nm and below, where extra circuitry can slow performance, boost the amount of power required to drive signals over longer, thinne... » read more

The Week In Review: Design
By Jesse Allen - 03 Mar, 2017 - Comments: 0

Legal Synopsys filed suit against Ubiquiti Networks and its project leader for "circumventing technological measures that effectively control access to Synopsys' software." The suit, filed in U.S. District Court in San Jose, claims that Ubiquiti used counterfeit keys obtained or created with tools from hacker websites to circumvent Synopsys' License Key system. Ubiquiti, based in San Jose, d... » read more

Dealing With Unintended Behavior
By Brian Bailey - 02 Mar, 2017 - Comments: 0

Functional verification was already tough enough, but having to identify behaviors that were never defined or intended opens up the search space beyond what existing tools are capable of handling. However, while you may not be able to eliminate unintended behaviors, a design team is not helpless. There are several steps that can be taken to reduce the likelihood of these problems getting int... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Test More Complex For Cars, IoT
By Ann Mutschler - 15 Feb, 2017 - Comments: 0

With increasing focus on safety-critical semiconductors—driven by ADAS, IoT, and security—functional safety concerns are going through the roof. Engineering teams are scrambling to determine how to conduct better in-field or online testing because test no longer can be an afterthought. This has been a common theme across the automotive ecosystem for the past few years, and as the automot... » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis
By Sankar Ramachandran - 09 Feb, 2017 - Comments: 0

As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages
By Ansys - 08 Feb, 2017 - Comments: 0

This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

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