12 Ways To Elevate Electronic Design Process Using PADS eBook


When using PADS Professional Premium, designers have access to standard PCB design functionality, such as schematic definition and physical layout, as well previously optional add-on features (now standard) and all of the latest cloud apps, including: Schematic definition: Access to everything you need: Circuit design and simulation, Component selection, library management, and signal integr... » read more

How Digital Twins Are Unlocking The Next Era Of Aerospace And Government Applications


By Ian Land, Jason Niatas, and Marc Serughetti Amidst changing economic waters and stringent manufacturing cycles, the aerospace, defense, and government landscape has seen an impressive technological evolution in the last few years. Innovations such as automating mission-critical systems and deploying advanced electronics in deep space exploration are expanding opportunities for government ... » read more

RISC-V Virtual Prototype


A new technical paper titled "Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype" was published by researchers at DFKI GmbH and University of Bremen. Abstract "RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet o... » read more

Best Practice: Scale-Resolving Simulations In Ansys CFD


While today’s CFD simulations are mainly based on Reynolds-Averaged Navier-Stokes (RANS) turbulence models, it is becoming increasingly clear that certain classes of flows are better covered by models in which all or a part of the turbulence spectrum is resolved in at least a portion of the numerical domain. Such methods are termed Scale-Resolving Simulation (SRS) models in this paper. This r... » read more

Recipe To Catch Bugs Faster Using Machine Learning


We all agree that verification and debug take up a significant amount of time and are arguably the most challenging parts of chip development. Simulator performance has consistently topped the charts and is a critical component in the verification process. Still, the need of the hour is to stretch beyond simulator speed to achieve maximum verification throughput and efficiency. Artificial in... » read more

Artificial Intelligence 101: It’s Math, Not Magic


The term artificial intelligence (AI) can be somewhat misleading. While the medium of intelligence is designed (and, in that sense, artificial or human-made), the intelligence itself is based on very real data. However, most people hear “AI” and think of futuristic robots or scenes from science fiction movies, not recognizing that the origin of AI is not fictional or magical — it’s math... » read more

Interactive Point-To-Point Resistance Simulations


Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

Better, Faster, And More Efficient Verification With The Power Of AI


Verification is often the most challenging part of the chip development process. Verification engineers have to balance quality of results (QOR) with time to results (TTR) and cost of results (COR). AI and ML technologies can play a significant part in increasing QOR, speeding up TTR, and reducing COR. This white paper outlines some of the major challenges for verification, describes how AI pro... » read more

Overview of Hardware-In-The-Loop (HIL) Simulations


This technical paper titled "Hardware-in-the-Loop Simulations: A Historical Overview of Engineering Challenges" was published by researchers at University of Maribor, Slovenia. Abstract: "The design of modern industrial products is further improved through the hardware-in-the-loop (HIL) simulation. Realistic simulation is enabled by the closed loop between the hardware under test (HUT) and ... » read more

Artificial Neural Network (ANN)-Based Model To Evaluate The Characteristics of A Nanosheet FET (NSFET)


This new technical paper titled "Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors" was published by researchers at SungKyunKwan University, Korea. Abstract: "In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generat... » read more

← Older posts Newer posts →