Week In Review: Design, Low Power

By Jesse Allen - 19 Jul, 2019 - Comments: 0

Tools & IP Arm has a new access and licensing model for its IP. Flexible Access allows SoC design teams to initiate projects before they license IP by paying a yearly fee for immediate access to a broad portfolio of technology, then paying a license fee only when they commit to manufacturing, followed by royalties for each unit shipped. IP available through Arm Flexible Access includes the... » read more

Week In Review: Design, Low Power

By Jesse Allen - 28 Jun, 2019 - Comments: 0

VESA published the DisplayPort 2.0 standard, which allows for a max payload of 77.37 Gbps, a 3X increase in data bandwidth performance compared to DisplayPort 1.4a. The latest release also includes capabilities to address beyond 8K resolutions, higher refresh rates and HDR support at higher resolutions, multiple display configurations, and support for 4K-and-beyond VR resolutions. It is backwar... » read more

How To Integrate An Embedded FPGA

By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Week In Review: Design, Low Power

By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Week In Review: Design, Low Power

By Susan Rambo - 15 Feb, 2019 - Comments: 0

Tools & IP Engineering simulation company ANSYS says thanks to new features in its ANSYS Twin Builder, product developers may be able save money in warranty and operational costs. The Twin Builder creates a digital twin of a systems in the field, enabling a convenient way to monitor and maintain systems remotely. The latest release adds predictive maintenance features for digital-twin runt... » read more

The Week In Review: Design

By Jesse Allen - 25 May, 2018 - Comments: 0

Tools & IP Cadence and National Instruments are teaming up with the aim of improving the semiconductor development and test process. The two companies are jointly working on common transistor models to ensure consistent simulation behavior between NI AWR Microwave Office circuit design software and the Cadence Spectre simulation platform. Cadence also launched the Virtuoso RF Solution for ... » read more

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Week In Review: Design, Low Power

Week In Review: Design, Low Power

How To Integrate An Embedded FPGA

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

The Week In Review: Design