Experts At The Table: The Future Of Verification


Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: The Future Of Verification


Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Lessons From Healthcare.gov


Patterning equipment uses software and needs software security. With that rather weak segue, I would like to discuss software projects, considering they are in the news at the moment. The stories about the healthcare.gov rollout bring back fond memories for all of us of software projects that have gone horribly wrong. On the list of things that guarantee a project will miss deadlines, late c... » read more

Don’t Quit Your Hardware Job


At the recent Intel Developers Forum I was struck with the prevalence of software-defined architectures. Topics covered software-defined networking, software-defined storage, and the software-defined data center. It seemed that the concept of software-defined infrastructure was everywhere. It’s not unique to IDF, however. I suspect that at the upcoming ARM TechCon the trend will continue, but... » read more

Virtual Prototypes For Early Software Development


In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prot... » read more

Blog Review: Oct. 23


It was a good week for good questions. Cadence’s Brian Fuller asks what applications dream about—or rather what’s their potential. In the context of technology development, that’s worth pondering. Mentor’s Mike Jensen asks what will you be remembered for. There are a couple other important addendums to that, such as how long you will be remembered. And perhaps even more important, ... » read more

The Week In Review: Oct. 18


By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

Experts At The Table: Debug


By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

What Can Go Wrong?


It’s no surprise that most corporate system-on-chip (SoC) design teams are dispersed throughout the world, with different functional teams often located in different countries and continents. For example, we have many customers whose SoC architecture is defined in the United States, but subsystems such as graphics and signal processing are designed elsewhere. Companies choose this approach in... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

← Older posts Newer posts →