tag: stacked die

‘What If’ In 3D
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling ‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node. When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design. ... » read more

Memory, Bandwidth And SoC Performance
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler High-end SoC architectures today can contain dozens of processing engines—multiple cores from MIPS and ARM, DSPs from Tensilica and CEVA, and even graphics processors. But with so many cores there also is a need for enormous amounts of memory, and that has been creating some unexpected design problems, In many cases so much memory is required for an SoC that some... » read more

Deja Vu All Over Again
By Ed Sperling - 27 Jan, 2011 - Comments: 0

Every now and then you get the feeling you’ve been here before, and with technology this is a persistent theme. Virtualization looks remarkably similar to time sharing, which is what most engineers in their 40s and 50s used when they were in college. And 3D stacking, particularly the 2.5D version, looks eerily like the old MCM, aka multi-chip module. There’s nothing wrong with resurre... » read more

Changes Ahead
By Ed Sperling - 18 Nov, 2010 - Comments: 0

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process. To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes ... » read more

Turn Up The Heat
By Ed Sperling - 15 Oct, 2010 - Comments: 0

For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high. It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the bes... » read more

The Unifying Promise Of 3D
By Ed Sperling - 27 May, 2010 - Comments: 0

There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump. Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chi... » read more

3D Integration: Extending Moore’s Law Into The Next Decade
By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

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