Stacking Logic On Logic

By Katherine Derbyshire - 21 Jul, 2016 - Comments: 0

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of each other. Three-dimensional chip stacking is most commonly seen in memory devices. Applied to logic, though, there are at least two different ways for integration to proceed. Completely process... » read more

Advanced Packaging Options, Issues

By Ed Sperling - 23 Jun, 2016 - Comments: 0

Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features. Cost has been one of the big deterrents for widespread adoption of [getkc id="82" kc_name="2.5D"]. Initially, the almost universal compla... » read more

Tech Talk: 2.5D Issues

By Ed Sperling - 25 Feb, 2016 - Comments: 0

Bill Isaacson, director of ASIC marketing at eSilicon, about how viable this packaging approach is, organic vs. inorganic interposers, where the problems are, thermal coupling, interposer cost, and what will change over the next couple years. » read more

Will 3D-IC Work?

By Ed Sperling - 11 Feb, 2016 - Comments: 3

Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

The Internet Of Power Also Benefits From Moore’s Law

By Imec - 21 Jan, 2016 - Comments: 0

By Jef Poortmans It may sound strange, but striving to achieve smaller dimensions with Moore’s Law is an important enabler for producing increasingly better solar cells, with a more elaborate technology toolbox (including ALD, epitaxy, etc.) Improved process steps are constantly being developed to achieve these small transistor dimensions (for growing material layers or to etch away str... » read more

Thinking Outside The Chip

By Ed Sperling - 14 Jan, 2016 - Comments: 0

Intel will begin adding 2.5D and 3D packaging into its processors, following the lead set by IBM and AMD in recognizing that new packaging approaches are essential for improving performance and lowering power. This shift won't derail the semiconductor industry's efforts to the reach future process nodes or continually shrink features, but it does add context for other factors that in... » read more

Changes In Chip Design

By Ernest Worthman - 07 Jan, 2016 - Comments: 0

We all know that sub-10nm is coming. But is that really what will define the next generation of semiconductors? Progress in semiconductor technology increasingly is not just about advancements in the hardware. It also involves advancements in applications and technologies peripheral to the devices themselves. That may sound counterintuitive, but going forward the technology, applications and... » read more

How To Choose A Processor

By Ann Mutschler - 10 Dec, 2015 - Comments: 0

Choosing a processor might seem straightforward at first glance, but like many engineering challenges it's harder than it looks. When is a CPU better than a GPU, MCU, DSP or other type of processor? And for what design—or part of a design? For decades, the CPU has been the default choice. “It is deliberately designed to be pretty efficient at all tasks, is straightforward to program, ... » read more

Memory Choices Grow

By Ed Sperling - 24 Nov, 2015 - Comments: 1

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Placing Bets On Future Technology

By Ed Sperling - 16 Nov, 2015 - Comments: 0

Marie Semeria, CEO of Leti, sat down with Semiconductor Engineering to talk about where the French research and technology organization is placing its future technology bets and what's behind those decisions. What follows are excerpts of that discussion. SE: It's becoming more difficult and expensive to shrink features, so where do we go next? Semeria: We see several areas that we believe... » read more

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