tag: Stanford University

Chip Industry’s Technical Paper Roundup: October 17
By Liz Allan - 17 Oct, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

Chip Industry Talent Shortage Drives Academic Partnerships
By Liz Allan - 16 Oct, 2023 - Comments: 0

Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

Chip Industry’s Technical Paper Roundup: September 26
By Liz Allan - 26 Sep, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=146 /] More Reading Technical Paper Library home » read more

Chip Industry’s Technical Paper Roundup: Sept 19
By Liz Allan - 19 Sep, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=141 /] More Reading Technical Paper Library home » read more

Formally Verifying Data-Oblivious Behavior In HW Using Standard Property Checking Techniques
By Technical Paper Link - 15 Sep, 2023 - Comments: 0

A technical paper titled “A Scalable Formal Verification Methodology for Data-Oblivious Hardware” was published by researchers at RPTU Kaiserslautern-Landau and Stanford University. Abstract: "The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-practice technique... » read more

Chip Industry Week In Review
By The SE Staff - 15 Sep, 2023 - Comments: 0

By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

Technical Paper Roundup: Sept 5
By Liz Allan - 05 Sep, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=132 /] (more…) » read more

An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification 
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “PEak: A Single Source of Truth for Hardware Design and Verification” was published by researchers at Stanford University. Abstract: "Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage d... » read more

Week In Review: Auto, Security, Pervasive Computing
By Liz Allan - 04 Aug, 2023 - Comments: 0

Hyundai, Samsung Catalyst Fund, and others invested a combined $100 million in Canada-based Tenstorrent to accelerate the design and development of AI chiplets and machine-learning software and allow the integration of AI into future Hyundai, Kia, and Genesis vehicles, plus other future mobilities such as robotics and advanced air mobility (AAM). The National Highway Traffic Safety Administr... » read more

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