Chip Industry’s Technical Paper Roundup: September 26

3D neuromorphic HW; NOR flash memory; improving thermal behavior of 2.5D SoPs; evaluating PQC HW accelerators; photonic-electronic smartNIC; quantum games; HW attacks on photonic AI accelerators; formally verifying data-oblivious behavior in HW.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference MIT
3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration KAIST and SK Hynix
Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications Seoul National University of Science and Technology and University of Seoul
REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal EPFL and HES-SO
PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators TU Darmstadt
The History of Quantum Games IBM Research and Aalto University
Integrated Photonic AI Accelerators under Hardware Security Attacks: Impacts and Countermeasures Ecole Polytechnique de Montreal and Colorado State University
A Scalable Formal Verification Methodology for Data-Oblivious Hardware RPTU Kaiserslautern-Landau and Stanford University

More Reading
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