tag: Stanford University

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Pinpointing the Dominant Component of Contact Resistance to Atomically Thin Semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resist... » read more

2D Semiconductors Make Progress, But Slowly
By Katherine Derbyshire - 28 Feb, 2022 - Comments: 2

Researchers are looking at a variety of new materials at future nodes, but progress remains slow. In recent years, 2D semiconductors have emerged as a leading potential solution to the problem of channel control in highly scaled transistors. As devices shrink, the channel thickness should shrink proportionally. Otherwise, the gate capacitance won’t be large enough to control the flow of cu... » read more

Power/Performance Bits: Nov. 24
By Jesse Allen - 24 Nov, 2021 - Comments: 0

Flexible, low power phase-change memory Engineers at Stanford University created a flexible phase-change memory. The non-volatile phase-change memory device is made up of germanium, antimony, and tellurium (GST) between two metal electrodes. 1s and 0s represent measurements of electrical resistance in the GST material. “A typical phase-change memory device can store two states of resis... » read more

Power/Performance Bits: Nov. 16
By Jesse Allen - 16 Nov, 2021 - Comments: 0

Light-emitting memory Researchers from Kyushu University and National Taiwan Normal University propose a 'light-emitting memory' based on a perovskite that can simultaneously store and visually transmit data. The team used the idea in conjunction with resistive RAM (RRAM), in which states of high and low resistance represent ones and zeros. "The electrical measurements needed to check the r... » read more

A graph placement methodology for fast chip design
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 24 Sep, 2021 - Comments: 1

Markets Worldwide semiconductor industry revenue is expected to grow 17.3% in 2021, compared with 10.8% in 2020, according to a new IDC report. Segment breakdown is as follows: [table id=5 /] “Semiconductor wafer prices increased in 1H21 and IDC expects increases to continue for the rest of 2021 due to material costs and opportunity cost in mature process technologies. Overall, IDC pre... » read more

Power/Performance Bits: Sept. 21
By Jesse Allen - 21 Sep, 2021 - Comments: 0

Catching switches in action Researchers from SLAC National Accelerator Laboratory, Stanford University, Hewlett Packard Labs, Penn State University, and Purdue University observed atoms moving inside an electronic switch as it turns on and off, revealing a state they suspect could lead to faster, more energy-efficient devices. "This research is a breakthrough in ultrafast technology and sci... » read more

Power/Performance Bits: Aug. 24
By Jesse Allen - 24 Aug, 2021 - Comments: 0

Low power AI Engineers at the Swiss Center for Electronics and Microtechnology (CSEM) designed an SoC for edge AI applications that can run on solar power or a small battery. The SoC consists of an ASIC chip with RISC-V processor developed at CSEM along with two tightly coupled machine-learning accelerators: one for face detection, for example, and one for classification. The first is a bin... » read more

New Power, Performance Options At The Edge
By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

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