tag: static analysis

Voltage Drop Now Requires Dynamic Analysis
By Karen Heyman - 08 Aug, 2024 - Comments: 0

At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed designs, where there was concern about supply lines delivering full voltage to transistors. As design margins have tightened in modern advanced designs, controlling voltage drop has become a requiremen... » read more

Shifting The Design Paradigm To Improve Verification Efficiency
By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

Chip-Package Co-Analysis Using Ansys RedHawk-CPA
By Ansys - 11 Nov, 2020 - Comments: 0

Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliab... » read more

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

Building A Safety Verification Flow
By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Power Challenges In ML Processors
By Brian Bailey - 12 Mar, 2020 - Comments: 0

The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Three Steps To Complete Reset Behavior Verification
By Chris Kwok - 14 Nov, 2019 - Comments: 0

By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

Addressing The Challenges Of Reset Verification In SoC Designs
By Mentor, a Siemens Business - 13 Nov, 2019 - Comments: 0

This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design. To read more, click here. » read more

Getting A Complete Picture Of Automotive Software
By Maximilian Odendahl - 28 Mar, 2019 - Comments: 0

The automotive industry is currently undergoing a major disruption, usually referred as the shift to automated, connected, electric, and shared vehicles (ACES[1]). Naturally, these changes also have a significant impact on the requirements of the hard- and software architectures of these new vehicles: Service-oriented software architectures used by multiple applications running on generali... » read more

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