tag: STATS ChipPAC

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications
By STATS ChipPAC - 11 Dec, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Shortages Hit Packaging Biz
By Mark LaPedus - 11 Dec, 2017 - Comments: 1

Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up earlier this year, but the problem has been growing and spreading since then. Supply imbalances reached a boiling point in the third and fourth quarters of this yea... » read more

ASE-SPIL Merger Wins Clearance
By Mark LaPedus - 24 Nov, 2017 - Comments: 0

Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries (SPIL) have finally received all anti-trust approvals for the proposed and long-awaited merger between the two IC packaging houses. The anti-trust approvals are a big step that clears the way for the creation of a combined ASE-SPIL entity. The ASE-SPIL entity, in turn, will create a powerhouse in the outsourced ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 10 Nov, 2017 - Comments: 0

Packaging and test A*STAR’s Institute of Microelectronics (IME) has formed a fan-out wafer-level packaging consortium comprising of OSATs, materials vendors, equipment suppliers and others. The group is called the FOWLP Development Line Consortium. As part of the announcement, Singapore’s IME has established a development line to accelerate the development of fan-out. Located in IME’s... » read more

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Challenges And Improvement Of Reliability In Advanced Wafer Level Packaging Technology
By STATS ChipPAC - 06 Nov, 2017 - Comments: 0

The number of WLCSP (wafer-level packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to wearable electronics and IoT products. Although WLCSSP is now a widely ac... » read more

New Power Concerns At 10/7nm
By Ann Mutschler - 16 Oct, 2017 - Comments: 1

As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

Toward System-Level Test
By Ed Sperling - 09 Oct, 2017 - Comments: 0

The push toward more complex integration in chips, advanced packaging, and the use of those chips for new applications is turning the test world upside down. Most people think of test as a single operation that is performed during manufacturing. In reality it is a portfolio of separate operations, and the number of tests required is growing as designs become more heterogeneous and as they ar... » read more

Reliability Of eWLB For Automotive Radar Applications
By STATS ChipPAC - 09 Oct, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Integrated Passives Market Gets Active
By Jeff Dorsch - 09 Oct, 2017 - Comments: 0

Integrated passive devices are seeing greater use within system-in-package technology and numerous applications, including the Internet of Things. The tiny devices are making their way into automotive electronics, consumer electronics, and health-care products, among other uses. Europe is leading the way in supplying IPDs, thanks to offerings from Infineon Technologies, STMicroelectronics, a... » read more

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