FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing

By Various Writers - 05 Mar, 2012 - Comments: 0

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking ... » read more

Model Report Card

By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler From its perspective as a leader implementing system level design methodology, STMicroelectronics is uniquely positioned to discuss issues and challenges related to the use of models in a variety of use cases. System-Level Design had the opportunity recently to discuss challenges in the modeling space with Jean-Marc Chateau, director of ST’s SPT (System Platforms a... » read more

Playing The Voltage Game

By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Thermal Modeling Held Back By Outdated Standards

By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Customer Perspective: STMicroelectronics

By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Customer perspective: STMicroelectronics

By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Mutschler With eight SoC designs currently in development on its 28nm manufacturing process, STMicroelectronics is well acquainted with the power challenges of making those designs work. LPE discussed these issues with Philippe Magarshack, ST’s Technology R&D Group Vice-President. What follows are excerpts of that conversation. LPE: What are the biggest challenges in getting ST... » read more

A Smart Filling Solution Yields Multiple Benefits

By Mentor Graphics Staff Writers - 01 Jul, 2011 - Comments: 0

By Jeff Wilson, A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manu... » read more

Tri-Gate’s Fallout

By Ed Sperling - 26 May, 2011 - Comments: 0

By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

The Multiple Faces Of Virtual Prototyping

By Ann Mutschler - 28 Apr, 2011 - Comments: 0

Virtual prototyping conjures either confusion or relief, so it should come as no surprise that some chip designers are still confused about the different types of prototypes on the market. “Virtual prototyping is going through a change right now,” explained Gary Smith, founder and chief analyst for Gary Smith EDA. “Today, users are using cycle-based tools to prototype sections of their... » read more

Gene’s Law Meets EDA

By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Pallab Chatterjee What will be the next major improvement that will cut power levels by an order of magnitude? That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law... » read more

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