tag: Synopsys

A Machine Learning-Based Approach To Formality Equivalence Checking
By Avinash Palepu - 29 Oct, 2020 - Comments: 0

By Avinash Palepu, Namrata Shekhar and Paula Neeley After a long and hard week, it is Friday night and you are ready to relax and unwind with a glass of wine, a sumptuous dinner and a great movie. You turn on Netflix and you expect that it will not only have plenty of pertinent suggestions for you, but also the most appropriate one based on all the previous movies and shows that you have wat... » read more

Is Hardware-Assisted Verification Avoidable?
By Brian Bailey - 29 Oct, 2020 - Comments: 1

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2020 - Comments: 0

Synopsys' Jacob Wilson provides some tips for how to prepare for the upcoming ISO SAE 21434 cybersecurity standard for road vehicles, starting with a security plan and understanding of risk levels. Cadence's Paul McLellan checks out Arm's first face-to-face wafer-bonded design, why it might be desirable, and some important aspects of how the proof-of-concept was developed. In a video, Men... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Performance and Power Tradeoffs At 7/5nm
By Ed Sperling - 27 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Oct, 2020 - Comments: 0

M&A Microchip Technology acquired LegUp Computing, a provider of a high-level synthesis compiler that automatically generates high-performance FPGA hardware from software. The LegUp HLS tool will be used alongside Microchip’s VectorBlox Accelerator Software Design kit and VectorBlox Neural Networking IP generator to provide a complete front-end solution stack for C/C++ algorithm develope... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 23 Oct, 2020 - Comments: 0

Automotive, automation General Motors is planning a third electric-vehicle plant. The former Saturn factory will make first fully electric Cadillac, in the former Saturn assembly line. Tesla is allowing some customers to beta test its Full Self-Driving (FSD), according to The Verge. The company pushed the software update to some early access customers to do some real world beta test. Some o... » read more

Making Chips To Last Their Expected Lifetimes
By Ed Sperling - 21 Oct, 2020 - Comments: 2

Chips are supposed to last their lifetime, but that expectation varies greatly depending upon the end market, whether the device is used for safety- or mission-critical applications, and even whether it can be easily replaced or remotely fixed. It also depends on how those chips are used, whether they are an essential part of a complex system, and whether the cost of continual monitoring and... » read more

Blog Review: Oct. 21
By Jesse Allen - 21 Oct, 2020 - Comments: 0

Rambus' Frank Ferro and IDC's Shane Rau compare the evolution of HBM and GDDR6, as well as the design tradeoffs and challenges of the two memory types. Mentor's Neil Johnson compares unit testing and formal property checking as first steps for verifying low-level RTL functionality. Synopsys' Patrick Carey considers the competing demands of delivering a product as soon as possible and maki... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

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