tag: Synopsys

Buying And Selling EDA Companies
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Buying companies is the easy part. Integrating them is the hard part. It’s also the point where most acquisitions that go awry actually run into problems. There are widely different strategies for how to accomplish integration. Sometimes they work, other times they don’t. And sometimes both companies are surprised by the outcome—for better or worse. “Either you thi... » read more

Established Nodes White Paper
By Various Writers - 26 Sep, 2013 - Comments: 0

A look at advanced place and route design for established process nodes. To download this white paper, click here. » read more

New Architectures Redefining The Data Center
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling The cost of powering and cooling data centers, coupled with a better understanding of how enterprise-level applications can utilize hardware more effectively, are spawning a new wave of changes inside of data centers. Data centers are always evolving, but in this sector that evolution is deliberate and sometimes painstakingly slow. In fact, each major shift tends to last a de... » read more

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

What Type of Insurance Do You Have?
By Tom De Schutter - 25 Sep, 2013 - Comments: 0

With the software development effort now accounting for roughly half of the overall SoC development cost, any delay on the software availability side can have a big impact on the SoC availability. As one engineer of a major semiconductor vendor expressed to me: “The SoC hardware is typically only available a couple of weeks before we want to announce and demonstrate it at a major show like CE... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Mask Data Prep Issues Compounding At 20nm
By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

Should EDA Heads Be In The Cloud?
By Brian Fuller - 19 Sep, 2013 - Comments: 0

Consider the following two comments about cloud computing and electronic design automation: “Over time everybody will move to the cloud in EDA at least in some extent.”—Raik Brinkmann, CEO of OneSpin Solutions. “We put a substantial effort into that, and of all the things we've done in the last 25 years this is probably the single one where the result is essentially zero. I don't ... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

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