tag: Synopsys

Architecturally Optimizing Memory Bandwidth
By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

The Week In Review: Design/IoT
By Jesse Allen - 27 Mar, 2015 - Comments: 0

Tools Mentor Graphics uncorked its new IC, package, and PCB co-design and optimization product. It includes a formal flow for ball grid array ball-map planning and optimization based on an "intelligent pin" concept and a multi-mode connectivity management system for cross-domain pin-mapping and system level cross-domain logical verification. Synopsys released a new tool for designing ASIP... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

Fast Followers And The Value of Virtual Prototyping
By Tom De Schutter - 26 Mar, 2015 - Comments: 0

I am writing this blog while traveling though China. In this country of opportunities, new electronics companies show up regularly and some of them are quickly growing to become leaders in their application domain. Of course it helps if your local market is as big, if not bigger, than the U.S. and European market combined. The advantage of being a fast follower is that you can learn from th... » read more

Patents And EDA Making Waves
By Brian Bailey - 26 Mar, 2015 - Comments: 0

If the old adage “may you live in interesting times” is true, then lawyers must be wondering if they should be very happy or scared. The rate at which [getkc id="16" comment="patent"] law, and patents in general, are changing should give everyone pause – including the future competitiveness of the United States and the value of patents to EDA. The World Intellectual Property Organizati... » read more

Busting The 3 Big Common Myths About Physical Prototyping
By Synopsys - 25 Mar, 2015 - Comments: 0

FPGA-based prototyping is so popular because it provides an economical way to functionally validate an ASIC design by creating a prototype that runs “at speed”, includes real world I/O, and enables early software development. Experienced prototypers are familiar with its benefits but there are still designers opposed to physical prototyping because they believe that it does not scale to sup... » read more

Blog Review: March 25
By Jesse Allen - 25 Mar, 2015 - Comments: 0

From brain implants that recover memories to color-shifting shoes, Ansys' Bill Vandermark features sci-fi visions of the future that are becoming reality in his top five tech picks of the week. In the world of embedded software, is a black box better? Mentor's Colin Walls questions whether the advantages that come of having full access to source code outweigh the downsides. Cadence's Neel... » read more

The Week In Review: Design/IoT
By Jesse Allen - 20 Mar, 2015 - Comments: 0

Mergers & Acquisitions Silvaco acquired Invarian, anticipating integration of Invarian's methodology will accelerate adoption of concurrent power-voltage-thermal analysis. Legal A U.S. District Court judge ordered Kilopass to pay $5.5 million to Sidense for legal fees incurred in Kilopass' patent infringement suit against Sidense. That lawsuit was  dismissed in 2012. Sidense filed... » read more

3D Effects At 20nm And Beyond
By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Challenges Mount For Patterning And Masks
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

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