Blog Review: March 18


How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

First Time Success And Cost Control


First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions NXP added to its list of recent acquisitions with Athena SCS, a UK-based provider of embedded software and cryptography for smart cards and NFC. Lattice Semiconductor closed its all-cash $606.6 million acquisition of Silicon Image. Tools Cadence unveiled the Innovus Implementation System. The physical implementation tool sports massively parallel architect... » read more

The Interconnected Web Of Power


Tradeoffs between area and timing used to follow fairly simple rules. You could improve timing by adding area, and occasionally find an architectural solution that would decrease both at the same time. With physical synthesis the relationship became a little more complicated because an increase in area, say to make a drive larger or add another buffer, might upset the layout. That, in turn, cou... » read more

Automotive Drives Novel IP Demands


In the past the automotive industry was a bit sleepy when it came to technologic innovations. Clearly, this is no longer the case. The automotive segment is now driving interesting capabilities and an unprecedented level of creativity by the IP and SoC engineering teams targeting this now-dynamic sector. Historically, electronics for automotive was very different from those aimed at consumer... » read more

One-To-Many: Shifting Left, Adding Gears


[getperson id="11034" comment="Aart de Geus"], chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], launched into high gear for his keynote talk at this year’s Design and Verification Conference (DVCon). The gathering attracted a record number of attendees, and it is estimated that about 350 people crammed into the room to listen to him talk about the shift left that is happening ... » read more

Extending UPF For Use In System-Level Design


Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

Rethinking The Cloud


Data center architectures have seen very few radical changes since the commercial introduction of the [getentity id="22306" comment="IBM"] System/360 mainframe in 1964. There have been incremental improvements in speed and throughput over the years, with a move to a client/server model in the 1990s, but from a high level this is still an environment where data is processed and stored centrally ... » read more

Blog Review: March 11


How are sensors like a scallop's eyes? Rambus' Patrick Gill guides you through day in the life of the mollusk to show how inspiration for IoT was found in the sea. Cadence's Dimitry Pavlovsky discusses some of the intricacies associated with creating VIP for processor interconnect systems such as CHI, and how other tools are necessary to complete the task. Following Google's warning of a ... » read more

Reality Check: A Guide To Understanding Optimized Processor Cores


The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation ... » read more

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