New Reliability Issues Emerge


By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

The Ubiquitous GPU


By Ann Steffora Mutschler No matter the application area, GPUs are likely playing a role like never before—even to accelerate EDA software algorithms. It’s no wonder given the ability of GPUs to handle parallel processing much more effectively than CPUs. And when coexisting in a heterogeneous system, GPUs allow the design team to maximize efficiency and performance by allocating tasks... » read more

The New Verification Landscape


By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Memory Gets Smarter


By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

A Team Is Only As Strong As Its Captain


By Tom De Schutter Last week I was in Cambridge, UK. Although the weather wasn’t great, which seems to be pretty standard every time I visit, it actually didn’t rain a whole lot. That was a victory in itself. On one of the evenings I was eating with some colleagues at a restaurant overlooking Parker’s Piece, a 25-acre square of grass near the center of Cambridge. Frequent visitors of ... » read more

From Design to Test: Developing High-Reliability MTP NVM


In developing high-quality and reliable MTP NVM, NVM IP providers must account for design and architectural considerations as well as comprehensive silicon testing. To help system-on-chip (SoC) designers select the highest reliability NVM IP, this white paper will review the key considerations involved in the entire process from design to test, including: key reliability specifications; designi... » read more

Experts At The Table: Performance Analysis


By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

The Week In Review: June 21


By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Merchant Photomask Makers Remain Relevant


By Jeff Chappell For many years the trend in the semiconductor industry with regard to photomasks and chipmakers was to shed captive mask operations in favor of merchant photomask suppliers. This reflected a larger trend all along the supply chain with many companies moving away from vertical integration as, consequently, the foundry model grew. "This was mainly driven by cost consideratio... » read more

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