tag: Synopsys

High-Quality Silicon With Cloud-Based Verification
By Rob van Blommestein - 15 Sep, 2023 - Comments: 0

New materials, vertically stacked architectures, and angstrom-level process technologies—the complexity of today’s SoCs continues to grow to meet the needs of demanding applications such as AI, autonomous vehicles, and high-performance computing. This trend only places greater pressure on verification, already notorious for being a significant bottleneck in chip development. Design teams... » read more

Using Virtual Metal Fill To Predict The Impact Of High Level Nets
By Vamsi Thatha - 14 Sep, 2023 - Comments: 0

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

Patterns And Issues In AI Chip Design
By Ed Sperling - 14 Sep, 2023 - Comments: 2

AI is becoming more than a talking point for chip and system design, taking on increasingly complex tasks that are now competitive requirements in many markets. But the inclusion of AI, along with its machine learning and deep learning subcategories, also has injected widespread confusion and uncertainty into every aspect of electronics. This is partly due to the fact that it touches so many... » read more

Managing P/P Tradeoffs With Voltage Droop Gets Trickier
By Ann Mutschler - 14 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop/IR drop with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight Technologies; Venkatesh Santhanagopalan, product manager at Movellus; Joe Davis, senior director for Calibre interfaces and mPower EM/IR... » read more

Understanding UVM Coverage For RISC-V Processor Designs
By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Blog Review: September 13
By Jesse Allen - 13 Sep, 2023 - Comments: 0

Siemens' Todd Westerhoff highlights the importance of signal integrity analysis in PCB design, challenges as simulation tools have become more sophisticated and difficult to use, and best practices like starting with a simple analysis problem. Synopsys' Rita Horner, Shekhar Kapoor, and William Ruby note that the power and thermal profiles of multi-die systems for HPC and the data center shou... » read more

Fab And Field Data Transforming Manufacturing Processes
By Gregory Haley - 12 Sep, 2023 - Comments: 0

The ability to capture, process, and analyze data in the field is transforming semiconductor metrology and testing, providing invaluable insight into a product's performance in real-time and under real-world conditions and use cases. Historically, data that encapsulates parameters such as power consumption, temperature, voltages, currents, timing, and other characteristics, was confined to d... » read more

Customizing IC Test To Improve Yield And Reliability
By Ed Sperling - 12 Sep, 2023 - Comments: 0

Testing the performance and power of semiconductors as they come off the production line is beginning to shift left in the fab, reversing a long-standing trend of assessing chips just prior to shipping. While this may sound straightforward, it's a difficult challenge which, if successful, will have broad implications for the entire design-through-manufacturing flow. Manufacturers typically g... » read more

Automotive Safety Requires PVT Monitoring IP Within Semiconductor ICs
By Rohan Bhatnagar - 12 Sep, 2023 - Comments: 0

The modern automobile, especially with the move toward more electrification, presents huge challenges to the designers of vehicular electronics. Gone are the days of mechanical issues and oil changes being primary concerns. Today’s automobile has a high number of semiconductor chips performing functions for self-driving autonomous systems, advanced driver assistance systems (ADAS), connectivi... » read more

Synopsys Timing Constraints Manager: Constraint Verification
By Synopsys - 11 Sep, 2023 - Comments: 0

Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy