tag: Synopsys

3D-ICs May Be The Least-Cost Option
By Brian Bailey - 30 Nov, 2023 - Comments: 1

When 2.5D and 3D packaging were first conceived, the general consensus was that only the largest semiconductor houses would be able to afford them, but development costs are quickly coming under control. In some cases, these advanced packages actually may turn out to be the lowest-cost options. With stacked die [1], each die is considered to be a complete functional block or sub-system. In t... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning
By Jim Schultz - 30 Nov, 2023 - Comments: 0

What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

Artificial Intelligence Wonderland
By Barry Pangrle - 30 Nov, 2023 - Comments: 0

Silicon Catalyst held its Sixth Annual Semiconductor Forum in Menlo Park on the SRI campus on November 9th. Richard Curtin, Managing Partner for Si Catalyst, opened the event with a reference to Arthur C. Clarke’s "2001: A Space Odyssey" and noted how remarkable it was that a novel written back in 1968 was able to foretell the direction of the computer industry over 50 years into the future. ... » read more

Making Heterogeneous Integration More Predictable
By Ed Sperling - 29 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Blog Review: November 29
By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Autonomous Vehicles: Not Ready Yet
By John Koon - 27 Nov, 2023 - Comments: 0

The swirl of activity around L4 and L5 vehicles has yet to result in a successful demonstration of an autonomous vehicle that can navigate the streets of a city or highway without incident, and there is a growing body of real-world data showing that much work still needs to be done. Robo-taxi trials in big cities such as San Francisco, Los Angeles, and soon San Diego, are proving that autono... » read more

What To Do About Electrostatic Discharge
By Ed Sperling - 20 Nov, 2023 - Comments: 0

Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

Chip Industry Week In Review
By The SE Staff - 17 Nov, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

What Is TCAD And Why It Is Essential For The Semiconductor Industry
By Shela Aboud - 16 Nov, 2023 - Comments: 0

Modern technology computer-aided design (TCAD) technologies have been around now for years. Yet, many semiconductor engineers still run experiments directly on wafers to examine chip fabrication processes and device operation. While it can be challenging to become proficient in TCAD, conducting experiments on wafers isn’t exactly easy, nor is it quick or cost-effective to do. As with so ma... » read more

Curvilinear Mask Patterning For Maximizing Lithography Entitlement
By Synopsys - 15 Nov, 2023 - Comments: 0

Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This paper includes practical solutions to overcome the computational challenges associated with this technique, as w... » read more

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