tag: Synopsys

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI
By Ed Sperling - 29 May, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Mastering AI Chip Complexity: Your Guide to First-Pass Silicon Success
By Synopsys - 28 May, 2025 - Comments: 0

This eBook provides a resource for innovators in the fast-changing realm of AI chip development. It delves into the opportunities and challenges of designing cutting-edge AI chips and chiplets, focusing on the transition from traditional monolithic architectures to multi-die and chiplet-based solutions. The content covers essential topics such as architectural exploration, silicon design, a... » read more

Blog Review: May 28
By Jesse Allen - 28 May, 2025 - Comments: 0

Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Chip Industry Week in Review
By The SE Staff - 23 May, 2025 - Comments: 0

Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Revolutionizing Semiconductor Development With GPU-Enhanced Atomistic Modeling
By Anders Blom - 22 May, 2025 - Comments: 1

There are many challenges in the development of a modern semiconductor chip, from front-end architecture simulation to final signoff. Volume manufacturing has its own set of challenges, while silicon lifecycle management (SLM) extends into field deployment and aging concerns. Underlying this entire development flow, however, lie the materials used to build the actual chips. Guiding the explorat... » read more

Cooling Chips Still A Top Challenge
By Bryon Moyer - 22 May, 2025 - Comments: 0

Increasing levels of semiconductor integration means more work needs to be done in smaller spaces, which in turn generates more heat that needs to be dissipated. Managing heat dissipation in advanced node dies and in multi-die assemblies is critical to their functionality and their longevity. And while much of the focus has been on improving power efficiency, which reduces the rate of power ... » read more

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

Blog Review: May 21
By Jesse Allen - 21 May, 2025 - Comments: 0

Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

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