Meeting The Material Challenges Of Nano-CMOS Electronics


A technical paper titled “Shockley-Read-Hall recombination and trap levels in In0.53 Ga0.47As point defects from first principles” was published by researchers at University of Glasgow and Synopsys Denmark. Abstract: "We present charge state transition levels of 23 intrinsic defects and dopant substitutions in the compound III-V semiconductor In0.53 Ga0.47 As, calculated with density func... » read more

Die-To-Die Security


Security concerns are growing as more chiplets or die are added into a package. There are more possible attack points, and data is becoming increasingly valuable, which makes a successful attack much more lucrative than in the past. Mike Borza, Synopsys scientist, talks about the impact of heterogeneous integration on security, what the risks are for multi-tenant data centers, and what happens ... » read more

Everyone’s A System Designer With Heterogeneous Integration


The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Chip Industry Week In Review


By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

Accelerating Analog Design Migration


Today’s electronic chips are commonly comprised of a mix of analog, RF, and digital components, with increasing functionalities, complexities, and numbers of transistors reaching the trillions. While the digital side of the house can take advantage of automated design implementation tools, the analog world has always been more about doing things manually and in a very “custom” way—which... » read more

Industry Pressure Grows For Simulating Systems Of Systems


Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

AI Drives Need For Optical Interconnects In Data Centers


An explosion of data, driven by more sensors everywhere and the inclusion of AI/ML in just about everything, is ratcheting up the pressure on data centers to leverage optical interconnects to speed up data throughput and reduce latency. Optical communication has been in use for several decades, starting with long-haul communications, and evolving from there to connect external storage to ser... » read more

What Happened To Portable Stimulus?


In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Universal Verification Methodology Coverage For Bluespec RISC-V Cores


Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal Verification Methodology (UVM) standard. This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solu... » read more

Blog Review: September 27


Siemens' Dirk Hartmann examines how a continual improvement in predictive capability processing and algorithms enables the evolution of simulation performance and highlights two areas that underpin most simulation tools. Synopsys' Ian Land, Jason Niatas, and Marc Serughetti note that digital twins can be used from the chip level through sub-systems and up to the system level to examine perfo... » read more

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