Week In Review: Semiconductor Manufacturing, Test


The U.S. Commerce Department  launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on ne... » read more

Week In Review: Design, Low Power


The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, ... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Renesas introduced a narrowband Internet of Things (NB-IoT) chipset and dev kit for the Indian market. The LTE NB-IoT modem chipset, the RH1NS200, was designed for Indian telecommunications carriers by targeting bands 1,3, 5 and 8 and by following India’s carrier-approved LTE protocol stack and software suite. Low power usage is built in — it has a low Power Saving Mode... » read more

EDA Makes A Frenzied Push Into Machine Learning


Machine learning is becoming a competitive prerequisite for the EDA industry. Big chipmakers are endorsing and demanding it, and most EDA companies are deploying it for one or more steps in the design flow, with plans to add much more over time. In recent weeks, the three largest EDA vendors have made sweeping announcements about incorporating ML into their tools at their respective user eve... » read more

Design Challenges Of High-Speed Wireline Transmitters


By Samad Parekh and Noman Hai The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25T (terabytes) to 50T and soon to 100T. The industry has chosen Ethernet to drive the switch market, using 112G SerDes technology today and next generation architectures being designed to operate at... » read more

True 3D-IC Problems


Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Designing For In-Circuit Monitors


In every application space the semiconductor ecosystem touches, in-circuit monitors and sensors are playing an increasing role in silicon lifecycle management and concepts around reliability and resiliency — both during design as well as in the field. The combination of true system-level design, in/on-chip monitors, and improved data analysis are expected to drastically improve reliability... » read more

New Standards Push Co-Packaged Optics


Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

Meeting The Major Challenges Of Modern Memory Design


Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5... » read more

Blog Review: April 26


Codasip's Tora Fridholm introduces the NimbleAI project, an effort to design a neuromorphic sensing and processing 3D integrated chip that implements an always-on sensing stage, highly specialized event-driven processing kernels and neural networks to perform visual inference of selected stimuli using the bare minimum amount of energy. Synopsys' Anjaneya Thakar discusses computational lithog... » read more

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