tag: Synopsys

Solving the AppSec Puzzle: Connecting AppSec To Your DevOps Pipeline
By Synopsys - 02 Aug, 2023 - Comments: 0

Integrating application security (AppSec) into your software development life cycle and DevOps pipeline is increasingly important in today’s development environment. Commonly referred to as “shifting left” or “shifting everywhere,” AppSec integration helps avoid the late-stage testing and development that can delay product releases or lead to overlooked risks being promoted into produ... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2023 - Comments: 0

Siemens' Katie Tormala points to the need for die attach thermal testing to ensure efficient removal of heat dissipation from power electronics components to prevent premature failure or thermal runaway. Synopsys's Dermott Lynch notes that over 30% of semiconductor failures are attributed to electrostatic discharge, with damage ranging from leakages and shorts to junction and metallization b... » read more

Battling Over Shrinking Physical Margin In Chips
By Ed Sperling - 31 Jul, 2023 - Comments: 0

Smaller process nodes, coupled with a continual quest to add more features into designs, are forcing chipmakers and systems companies to choose which design and manufacturing groups have access to a shrinking pool of technology margin. In the past margin largely was split between the foundries, which imposed highly restrictive design rules (RDRs) to compensate for uncertainties in new proces... » read more

Reducing Chip Test Costs With AI-Based Pattern Optimization
By Rahul Singhal - 31 Jul, 2023 - Comments: 0

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production throughput demands. This is a huge issue for chip producers, since high pin counts, blazingly ... » read more

Week In Review: Design, Low Power
By SE Staff - 28 Jul, 2023 - Comments: 0

Arm is helping to address the ongoing talent shortage through its newly announced Semiconductor Education Alliance, with a long list of partners, including Arduino, Cadence, Cornell University, Semiconductor Research Corp., STMicroelectronics,Synopsys, Taiwan Semiconductor Research Institute, the All-India Council for Technical Education, and the University of Southampton. The Alliance... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

The Good And Bad Of Chip Design On Cloud
By Ann Mutschler - 27 Jul, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about how the shift toward chip design on cloud has sped up, whether the benefits of cloud are realized in chip design, and some of the most pressing challenges to chip design on cloud today, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Syst... » read more

New Technology Accelerates Multi-Die System Simulation
By Taruna Reddy - 27 Jul, 2023 - Comments: 0

AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

Blog Review: July 26
By Jesse Allen - 26 Jul, 2023 - Comments: 0

Siemens' Chris Spear shows how to make a group of specialized classes in SystemVerilog. Synopsys' Guy Cortez and Randy Fish consider what a silicon lifecycle management strategy looks like for SoCs deployed in HPC and data center environments. Cadence's Veena Parthan provides a primer on writing Python scripts for Fidelity, including API descriptions and different sets of packages to acce... » read more

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