Accelerating Circuit Simulation 10x With GPUs


By Samad Parekh (Synopsys) and Srinivas Kodiyalam (NVIDIA) Many aspects of semiconductor design and verification have an ever-growing “need for speed” that has outpaced the performance improvements available by running on CPUs. Electronic design automation (EDA) companies have responded by creating smarter software algorithms to improve simulation time, sometimes at the expense of relaxe... » read more

Blog Review: March 9


Arm's Ajay Joshi investigates how to select the right benchmark for CPUs used in the Home device market, such as digital television and set-top box/over-the-top devices. Ansys' Jon Kordell checks out how reliability physics simulations and physical component characterization can support component swapping in high-reliability applications when the original part is unavailable due to supply ch... » read more

Software-Driven and System-Level Tests Drive Chip Quality


Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II


By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Auto Chipmakers Dig Down To 10ppb


How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism


Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more

Verifying Side-Channel Security Pre-Silicon


As security grows in importance, side-channel attacks pose a unique challenge because they rely on physical phenomena that aren’t always modeled for the design verification process. While everything can be hacked, the goal is to make it so difficult that an attacker concludes it isn't worth the effort. For side-channel attacks, the pre-silicon design is the best place to address any known ... » read more

Why Banks Should Be More Worried About Security


At about 10:30 a.m. on Friday, Feb. 5, 2016, Jubail Bin-Huda, a joint director of Bangladesh Bank, and a colleague went to pick up the latest Society for Worldwide Interbank Financial Telecommunication (SWIFT) acknowledgement messages from the printer. When they got to the printer, they found nothing had been printed. They restarted the printer manually, but it still didn't work. They had no... » read more

Meet Both Security And Safety Needs In New Automotive SoCs


With advances in hardware and software, smart vehicles are improving with every generation. Capabilities that once seemed far-off and futuristic—from automatic braking to self-driving features—are now either standard or within reach. However, as vehicle architectures evolve, the ways that both security and safety can be addressed at the system-on-chip (SoC) level also must evolve. Cars a... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

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