tag: Synopsys

Improving PPA In Complex Designs With AI
By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Feb, 2022 - Comments: 0

Nvidia's proposed acquisition of Arm is officially off. The deal faced significant pushback from regulatory agencies in the UK, USA, and Europe, which feared it would reduce or limit competition in areas like data center. Nvidia indicated it would continue working with Arm, and it will retain a 20-year Arm license. (SoftBank will retain the $1.25 billion prepaid by Nvidia.) SoftBank said it wil... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 11 Feb, 2022 - Comments: 0

Pervasive computing, IoT and 5G Infineon added to its NFC (near-field communications) IP by acquiring NFC patent portfolios from France Brevets and Verimatrix. “With this acquisition, Infineon further strengthens its IP and technology portfolio, specifically in our leadership markets for security and connectivity for the IoT,” said Thomas Rosteck, president of Infineon’s Connected Secure... » read more

Why Data Center Power Will Never Come Down
By Bryon Moyer - 10 Feb, 2022 - Comments: 3

Data centers have become significant consumers of energy. In order to deal with the proliferation of data centers and the servers within them, there is a big push to reduce the energy consumption of all data center components. With all that effort, will data center power really come down? The answer is no, despite huge improvements in energy efficiency. “Keeping data center power consum... » read more

AI Everywhere: Accelerating Chip Design At Every Node
By Geetha Rangarajan - 10 Feb, 2022 - Comments: 0

Over the last few years, artificial Intelligence (AI) has increasingly played a significant role in the chip development process. But, when people talk about AI-designed chips, it is usually in the context of the latest, cutting-edge designs manufactured at advanced process nodes (7/5nm and smaller) and for good reason. Such designs constantly push the bounds of power, performance, and area (PP... » read more

Spreadsheets: Still Valuable, But More Limited
By Brian Bailey - 10 Feb, 2022 - Comments: 1

Spreadsheets have been an invaluable engineering tool for many aspects of semiconductor design and verification, but their inability to handle complexity is squeezing them out of an increasing number of applications. This is raising questions about whether they still have a role, and if so, how large that role will be. There are two sides to this issue. On one side are the users who see them... » read more

Design Challenges Increasing For Mixed-Die Packages
By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

Calibrate And Configure Your Power Management IC With NVM IP
By Synopsys - 09 Feb, 2022 - Comments: 0

Power Management Integrated Circuits (PMICs) are the first to turn on and the last to turn off in a system. They perform the task of delivering the right voltage to component chips by regulating or boosting the voltage levels to the component chips. Some PMICs are configured once at the factory and an area-efficient OTP NVM is the best choice. When a PMIC is expected to be re-configured mult... » read more

Blog Review: Feb. 9
By Jesse Allen - 09 Feb, 2022 - Comments: 0

Arm's Mark Inskip walks through how the Morello program built a demonstration of the architecture that enables fine-grained memory protection and highly scalable software compartmentalization based on the CHERI (Capability Hardware Enhanced RISC Instructions) architectural model, from IP development and SoC design to creating software and a demonstration board. Synopsys' Plamen Asenov and su... » read more

Unknowns Driving Up The Cost Of Auto IC Reliability
By Ed Sperling - 08 Feb, 2022 - Comments: 2

Automotive chipmakers are considering a variety of options to improve the reliability of ICs used for everything from sensors to artificial intelligence. But collectively they could boost the number of process steps, increase the time spent in manufacturing and packaging, and stir up concerns about the amount of data that needs to be collected, shared, and stored. Accounting for advanced pro... » read more

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