Hybrid Simulation Picks Up Steam

By Ann Mutschler - 26 Jan, 2017 - Comments: 0

As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP

By Cadence - 09 Nov, 2016 - Comments: 0

The proposed IEEE 802.11ah wireless networking protocol is designed to meet the requirements of Internet of Things (IoT) connectivity, providing the bit rate, security, and low power required for these types of connected devices. Design requirements for 802.11ah access point and clients vary widely, even though all implement the same mathematical algorithm. In this paper, we will discuss how... » read more

Tech Talk: Earlier Software

By Ed Sperling - 02 Nov, 2016 - Comments: 0

Malte Doerper, senior manager of product management at Synopsys, talks about the big "shift left" for software, where the problems crop up, and how to save as much as a year of development time with automation and better methodologies. Related Stories Bridging Hardware And Software The need for concurrent hardware-software design and verification is increasing, but are engine... » read more

Gaps In The Verification Flow

By Brian Bailey - 01 Nov, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Fast, Accurate, And Standards-Based

By Pat Sheridan - 01 Nov, 2016 - Comments: 0

Unlike the loosely timed models used for software development, which rely on a high level of abstraction to simulate as fast as possible, the communication between the architecture models in a virtual prototype for early performance analysis requires timing to be modeled more accurately. This tradeoff can seem like a big leap to some, spanning the gap from SystemC TLM-2.0 LT (loosely timed) ... » read more

Too Big To Simulate?

By Ann Mutschler - 27 Oct, 2016 - Comments: 2

With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

Early Power Modeling Using SystemC And TSMC System-PPA

By Kurt Shuler - 10 Oct, 2016 - Comments: 0

Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

To Emulate Or Prototype?

By Krzysztof Szczur - 28 Jul, 2016 - Comments: 0

FPGA Prototyping is more challenging than emulation. Yet for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation. Emulation also has benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugg... » read more

What’s Next For UVM?

By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Cars, Security, And HW-SW Co-Design

By Jeff Dorsch - 07 Jul, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

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tag: SystemC

Hybrid Simulation Picks Up Steam

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP

Tech Talk: Earlier Software

Gaps In The Verification Flow

Fast, Accurate, And Standards-Based

Too Big To Simulate?

Early Power Modeling Using SystemC And TSMC System-PPA

To Emulate Or Prototype?

What’s Next For UVM?

Cars, Security, And HW-SW Co-Design

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