tag: TCAD

Artificial Neural Network (ANN)-Based Model To Evaluate The Characteristics of A Nanosheet FET (NSFET)
By Technical Paper Link - 02 Sep, 2022 - Comments: 0

This new technical paper titled "Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors" was published by researchers at SungKyunKwan University, Korea. Abstract: "In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generat... » read more

TCAD-Based Radiation Modeling Technique For Reliable Aerospace Chips
By Ian Land - 28 Jul, 2022 - Comments: 0

By Ian Land and Ricardo Borges We demand a lot from the electronic components that bring our devices and systems to life. This is particularly true when it comes to semiconductors for space applications. From satellites to spacecraft, aerospace and defense equipment must tolerate the most extreme of operating conditions in order to perform their jobs safely and reliably. How do you ensure... » read more

Improving Machine Learning-Based Modeling of Semiconductor Devices by Data Self-Augmentation
By Technical Paper Link - 24 Mar, 2022 - Comments: 0

Abstract: "In the electronics industry, introducing Machine Learning (ML)-based techniques can enhance Technology Computer-Aided Design (TCAD) methods. However, the performance of ML models is highly dependent on their training datasets. Particularly in the semiconductor industry, given the fact that the fabrication process of semiconductor devices is complicated and expensive, it is of grea... » read more

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

A New Vision For Memory Chip Design And Verification
By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Modeling Chips From Atoms To Systems
By Ann Mutschler - 26 Aug, 2021 - Comments: 1

Complexity in hardware design is spilling over to other disciplines, including software, manufacturing, and new materials, creating issues for how to model more data at multiple abstraction levels. Challenges are growing around which abstraction level to use for a particular stage of the design, when to use it, and which data to include. Those decisions are becoming more difficult at each ne... » read more

Influence Of SiGe On Parasitic Parameters in PMOS
By Coventor - 27 Sep, 2019 - Comments: 0

In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow p... » read more

Connecting Wafer-Level Parasitic Extraction And Netlisting
By Michael Hargrove - 18 Apr, 2019 - Comments: 0

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In thi... » read more

Five DAC Keynotes
By Brian Bailey - 17 Jul, 2018 - Comments: 0

The ending of Moore's Law may be about to create a new golden age for design, especially one fueled by artificial intelligence and machine learning. But design will become task-, application- and domain-specific, and will require that we think about the lifecycle of the products in a different way. In the future, we also will have to design for augmentation of experience, not just automation... » read more

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