tag: TechSearch International

Chip Industry Technical Paper Roundup: Sept. 9
By Linda Christensen - 09 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=354 /] More ReadingTechnical Paper Library home » read more

ECTC 2024 Session Readout: Advancement of Metrology
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A Electronic Components and Technology Conference (ECTC) session report titled "2024 ECTC Special Session Report: Advancing Metrology for Next-Generation Microelectronics" was published by NIST, Binghamton University, and TechSearch International. Abstract: "Metrology plays a pivotal role in semiconductor research, manufacturing, packaging and assembly. It is critical to the success of this... » read more

Fan-Out Packaging Gets Competitive
By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 14 Jan, 2022 - Comments: 0

Chipmakers, OEMs TSMC reported sales of $15.736 billion for the fourth quarter of 2021, up 5.7% sequentially. Net income grew 6.4% quarter-over-quarter. In the fourth quarter, shipments of 5nm accounted for 23% of total wafer revenues, while 7nm accounted for 27%. In the first quarter of 2022, TSMC’s sales are expected to be between $16.6 billion to $17.2 billion. TSMC also expects its 20... » read more

Expanding Advanced Packaging Production In The U.S.
By Mark LaPedus - 05 Jan, 2022 - Comments: 0

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

System-In-Package Thrives In The Shadows
By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Blog Review: March 3
By Jesse Allen - 03 Mar, 2021 - Comments: 0

Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

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