Communication Is Key To Finding And Fixing Bugs In ICs

By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?

By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix. Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures

By Technical Paper Link - 18 Apr, 2022 - Comments: 0

Abstract "This paper describes a novel approach to assess detection mechanisms and their diagnostic coverage, implemented using embedded software, designed to identify random hardware failures affecting digital components. In the literature, many proposals adopting fault injection methods are available, with most of them focusing on transient faults and not considering the functional safety st... » read more

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures

By Technical Paper Link - 01 Apr, 2022 - Comments: 0

New research paper from Politecnico di Torino. Abstract: "This paper describes a novel approach to assess detection mechanisms and their diagnostic coverage, implemented using embedded software, designed to identify random hardware failures affecting digital components. In the literature, many proposals adopting fault injection methods are available, with most of them focusing on transien... » read more

The Next Generation of Testbench Debug Productivity

By Synopsys - 08 Jun, 2021 - Comments: 0

It is widely accepted that verification consumes at least sixty percent of time and resources on most semiconductor development projects. This statistic has been borne out by many industry surveys over the last twenty years. Verification technology has had to evolve to accommodate ever larger and more complex designs. Innovations such as constrained-random simulation and the Universal Verificat... » read more

Bridging the IP Divide

By Brian Bailey - 18 May, 2016 - Comments: 1

IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

Bridging The IP Divide

By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: test bench

Communication Is Key To Finding And Fixing Bugs In ICs

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures

The Next Generation of Testbench Debug Productivity

Bridging the IP Divide

Bridging The IP Divide