tag: test

Total Critical Area For Optimizing Test Patterns
By Ed Sperling - 19 Oct, 2021 - Comments: 0

Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

The Everything New Syndrome
By Ed Sperling - 12 Oct, 2021 - Comments: 0

Technology is all about the latest features, the fastest processing, with the lowest power. While that sounds great in marketing pitch, any or all of those factors don't necessarily equate to a better product or long-term user satisfaction. There's a reason semiconductor companies are conservative by nature. They want to know that when they spend tens or hundreds of millions of dollars on a ... » read more

Manage Scaling Challenges For Silicon Success
By Siemens EDA - 12 Oct, 2021 - Comments: 0

Semiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation. This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling... » read more

Inspecting, Testing, And Measuring SiC
By Patrick Waurzyniak - 12 Oct, 2021 - Comments: 0

Achieving the auto industry's stringent zero defect goals is becoming a big challenge for makers of silicon carbide substrates, which are struggling to achieve sufficient yields and reliability as they migrate from 150mm to 200mm wafers and shift their focus away from pure silicon. SiC is a combination of silicon and harder carbide materials, and it has emerged as a key technology for batter... » read more

One Test Is Not Always Enough
By Anne Meixner - 12 Oct, 2021 - Comments: 0

To improve yield, quality, and cost, two separate test parameters can be combined to determine if a part passes or fails. The results gleaned from that approach are more accurate, allowing test and quality engineers to fail parts sooner, detect more test escapes, and ultimately to improve yield and reduce manufacturing costs. New data analytic platforms, combined with better utilization of s... » read more

Don’t Let X Be A Problem For Logic BIST
By Rahul Singhal - 12 Oct, 2021 - Comments: 0

By Rahul Singhal and Giri Podichetty A failure in the operation of integrated circuits (ICs) or chips deployed in safety-critical applications such as automotive, medical, and aerospace could have catastrophic consequences. These failures could stem from defects in the chip that escaped manufacturing tests or from transient faults that can occur during system operation due to factors such as... » read more

PCB And IC Technologies Meet In The Middle
By Bryon Moyer - 12 Oct, 2021 - Comments: 1

Surface-mount technology (SMT) is evolving far beyond its roots as a way of assembling packaged chips onto printed circuit boards without through-holes. It is now moving inside packages that will themselves be mounted on PCBs. But SMT for advanced packages isn’t the same as the SMT we’ve been used to. “Many systems include multiple ASICs, a lot of memory, and that's all integrated i... » read more

Packetized Test At The International Test Conference 2021
By Geir Eide - 12 Oct, 2021 - Comments: 0

At this year’s International Test Conference (October 10-15, 2021), Siemens Digital Industries Software is showcasing IC test and lifecycle management technologies that address the key scaling challenges facing the semiconductor industry now and in the future. The two main topics from Tessent at ITC are: The rapid adoption of packetized test strategies to address design and system... » read more

Challenges With Chiplets And Packaging
By Mark LaPedus - 15 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

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