tag: test

Enabling The Next Step In IC Test And Monitoring
By Siemens EDA - 21 Apr, 2021 - Comments: 0

Product lifecycle management (PLM) is a well-established concept across many industries that aims to manage the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. More recently, these principles are being applied by the semiconductor industry because electronics continue to p... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

MIPI D-PHY RX⁺: An Optimized Test Configuration
By Mixel - 07 Apr, 2021 - Comments: 0

With the proliferation of the mobile platform, the accelerating adoption of MIPI beyond the traditional mobile platform and into safety related applications, testability of MIPI® PHY is becoming a key requirement. While the D-PHY is the MIPI PHY with the widest adoption in the industry today, the RX+ is a D-PHY receiver configuration optimized for full-speed production testing. The presentatio... » read more

AI In Inspection, Metrology, And Test
By Susan Rambo And Ed Sperling - 06 Apr, 2021 - Comments: 0

AI/ML is creeping into multiple processes within the fab and packaging houses, although not necessarily for the purpose it was originally intended. The chip industry is just beginning to learn where AI makes sense and where it doesn't. In general, AI works best as a tool in the hands of someone with deep domain expertise. AI can do certain things well, particularly when it comes to pattern m... » read more

How Heterogeneous ICs Are Reshaping Design Teams
By Ed Sperling - 31 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Meeting The Challenges Of 5G RF Production Test Services
By Vineet Pancholi - 18 Mar, 2021 - Comments: 0

Implementation of the 5G radio frequency (RF) standard is increasing rapidly [1]. Over the past four to six quarters, there has been an increased focus on publications and products that have been introduced to the marketplace. Some of the more popular RF eco-system applications include cellphone, Wi-Fi, automotive, Internet of Things (IoT), location services, and more. Wi-Fi and cellphone servi... » read more

Development Of Digital Controlled Technology For High Voltage DC Testing
By Advantest - 09 Mar, 2021 - Comments: 0

In recent years, the demand for low power devices has increased due to issues related to global environmental protection. As a result, the demand for high-voltage power devices has also increased. To test such devices, test equipment that can handle high-voltage devices (hereinafter referred to as “test equipment”) is required. In addition, test time must be shortened to reduce manufacturin... » read more

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Big Challenges In Verifying Cyber-Physical Systems
By Ed Sperling - 25 Feb, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss cyber-physical systems and how to verify them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architect specialist at STMicroelectronics. This discussion was... » read more

Part Average Tests For Auto ICs Not Good Enough
By Anne Meixner - 24 Feb, 2021 - Comments: 0

Part Average Testing (PAT) has long been used in automotive. For some semiconductor technologies it remains viable, while for others it is no longer good enough. Automakers are bracing for chips developed at advanced process nodes with much trepidation. Tight control of their supply chains and a reliance upon mature electronic processes so far have enabled them to increase electronic compone... » read more

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