tag: test

Using Critical Area To Boost Automotive IC Test Quality
By Ron Press - 03 Sep, 2020 - Comments: 0

To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per million (DPPM), DFT engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types o... » read more

Critical Area-Based Test Pattern Optimization For High-Quality Test
By Mentor, a Siemens Business - 02 Sep, 2020 - Comments: 0

Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

5G Brings New Testing Challenges
By Bryon Moyer - 11 Aug, 2020 - Comments: 0

As 5G nears commercial reality, makers of chips and systems that will support 5G will need to take on the standard burden of characterizing and testing their systems to ensure both performance and regulatory adherence. Millimeter-wave (mmWave) and beamforming capabilities present the biggest testing challenges. “5G is expected to have the extended coverage plus the bandwidth to harness ... » read more

Advanced Packaging, Heterogeneous Integration And Test
By FormFactor - 11 Aug, 2020 - Comments: 0

Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test. At this exciting time in the industry, open engagement between customers and suppliers has never been more important for the test community. Click here to read more. » read more

Next Challenge: Parts Per Quadrillion
By Ed Sperling - 29 Jul, 2020 - Comments: 0

Requirements for purity of the materials used in semiconductor manufacturing are being pushed to unprecedented — and increasingly unprovable — levels as demand for reliability in chips over increasingly longer lifetimes continues to rise. And while this may seem like a remote problem for many parts of the supply chain, it can affect everything from availability of materials needed to make t... » read more

Next Challenge: Known Good Systems
By Ed Sperling - 07 Jul, 2020 - Comments: 0

The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge. This doesn't mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme t... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Data Becomes Key For Next-Gen Chips
By Susan Rambo And Ed Sperling - 07 Jul, 2020 - Comments: 1

Data has become vital to understanding the useful life of a semiconductor — and the knowledge gleaned is key to staying competitive beyond Moore’s Law. What's changed is a growing reliance earlier in the design cycle on multiple sources of data, including some from further right in the design-through-manufacturing flow. While this holistic approach may seem logical enough, the semiconduc... » read more

Using Built-In Self-Test Hardware To Satisfy ISO 26262 Safety Requirements
By Mentor, a Siemens Business - 30 Jun, 2020 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. The ICs for safety-critical applications need to meet the ISO 26262 standard for functional safety. Among the challenges in the design flow has been aligning the metrics for design-for-test and for functional safety. This paper describes using logic built-in-self-test as b... » read more

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