tag: test

EDT Test Points
By Mentor, a Siemens Business - 22 Jan, 2015 - Comments: 0

Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, cal... » read more

Blog Review: Dec. 31
By Ed Sperling - 31 Dec, 2014 - Comments: 0

Mentor's J. VanDomelen zeroes in on the two most interesting discoveries from the Philae comet landing. So what was that "eerie cyclical clicking" sound? Synopsys' Ray Varghese digs into basic coherent transaction testing for AXI/ACE compliant interconnects. You might want to put on another pot of coffee. Cadence's Brian Fuller offers some deep insights into synthesis, verification and te... » read more

How To Test IoT Devices
By Mark LaPedus - 11 Dec, 2014 - Comments: 0

At a recent event, test experts said the IC industry needs a new paradigm in testing chips for the [getkc id="76" comment="Internet of Things"] (IoT). The message was fairly simple to interpret. Existing automatic test equipment (ATE) is well suited to test today’s digital, analog, and mixed-signal chips, though it may be ill-equipped or too expensive to test IoT-based devices. But wha... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

EDA Vendors Prepare For 7nm
By Ann Mutschler - 18 Sep, 2014 - Comments: 0

It’s not too early to begin looking at design tools for the 7nm, even though the node is not expected to be production-ready until later this decade. While still in the early stages, foundries already in development with leading EDA companies, even though the water remains murky at this point. “7nm right now is in early definition, so we don't know exactly what it will be,” observed... » read more

Manufacturing Test Robustness
By Kiran Vittal - 11 Sep, 2014 - Comments: 0

The recent 6.0 earthquake near Napa California caused close to $50 million in damages to the wineries and property in the region. The San Francisco bay area is accustomed to earthquakes and hence structural engineers design buildings to bear high intensity earthquakes amongst other natural disasters. The damage to property would have been much higher if not due to the strict guidelines followed... » read more

Interpreting UPF For A Mixed-Signal Design Under Test
By Mentor, a Siemens Business - 23 Jul, 2014 - Comments: 0

This paper describes a methodology (as implemented in the Mentor Graphics Questa ADMS mixed-signal simulator) for interpreting the Unified Power Format (UPF) for analog mixed-signal designs coded in Verilog-AMS, VHDL-AMS, or SPICE. No changes to the UPF syntax or file are required. A complete implementation and a demonstration of its use in a sample case are provided as proof of concept. To ... » read more

More Effective Test: Slack-Based Transition Delay
By Synopsys - 23 Jul, 2014 - Comments: 0

Semiconductor companies have come to rely on delay testing to attain high defect coverage of manufactured digital integrated circuits (ICs). Delay testing uses transition delay (TD) patterns created by automatic test pattern generation (ATPG) tools to target subtle manufacturing defects in fabricated designs. Although standard TD testing improves defect coverage beyond levels stuck-at patterns ... » read more

Designing And Testing FinFET-based IC Designs
By Mentor Graphics Staff Writers - 19 Jun, 2014 - Comments: 0

By Carey Robertson and Steve Pateras The emergence of FinFET transistors has had a significant impact on the IC physical design and design-for-test flows. The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. The BSIM Group of the UC Berkeley Device Group has ... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

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