tag: thermal

Shifting Left: Early Multi Physics Analysis For STCO
By Per Viklund - 24 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

High Thermal Die-Attach Paste Development For Analog Circuits
By Amkor - 16 Jun, 2021 - Comments: 0

In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Thermal Floorplanning For Chips
By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Mapping Heat Across A System
By Ann Mutschler - 13 May, 2021 - Comments: 0

Thermal issues are becoming more difficult to resolve as chip features get smaller and systems get faster and more complex. They now require the integration of technologies from both the design and manufacturing flows, making design for power and heat a much broader problem. This is evident with the evolution of a smart phone. Phones sold 10 years ago were very different devices. Functionali... » read more

How Heterogeneous ICs Are Reshaping Design Teams
By Ed Sperling - 31 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Modeling PCBs For Common Causes Of Failure
By Theresa Duncan - 11 Feb, 2021 - Comments: 0

By Theresa Duncan and Michael Blattau When designing printed circuit boards (PCBs), keep in mind the major causes of electronic failure: thermal cycling, vibration, and mechanical shock and drop. You can perform a variety of physical tests to determine how and why electronics fail, however, a much faster and cost-effective solution is PCB modeling and simulation. When simulation is used i... » read more

Improving Automotive Electronic Hardware With SAE J3168
By Theresa Duncan - 14 Jan, 2021 - Comments: 0

By Theresa Duncan and Craig Hillman The race is on for fully autonomous vehicles. Industry giants like Tesla, Google, Uber and almost all major automotive companies are competing to deliver state-of-the-art self-driving vehicles. However, the development of new, cutting-edge technologies demands a similar wave of reliability, repairability and warranty standards that automotive manufactur... » read more

112G SerDes Reliability
By Ed Sperling - 05 Oct, 2020 - Comments: 0

Priyank Shukla, product marketing manager at Synopsys, digs into 112Gbps SerDes, why it’s important to examine the performance of these devices in the context of a system, what is acceptable channel loss, and how density can affect performance, power and noise. » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

Managing Worst Case Power Conditions
By Richard McPartland - 13 Aug, 2020 - Comments: 0

With each new technology node, especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal activity and supply variation. Dennard scaling brought about the ability for power to be scaled down with each successive node so that power per unit area stayed roughly constant. However, as highlighted by John Hennessy at last y... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy