tag: through-silicon vias

Processing In Memory
By Ed Sperling - 05 Sep, 2018 - Comments: 1

Adding processing directly into memory is getting a serious look, particularly for applications where the volume of data is so large that moving it back and forth between various memories and processors requires too much energy and time. The idea of inserting processors into memory has cropped up intermittently over the past decade as a possible future direction, but it was dismissed as an e... » read more

Old Vs. New Packages
By Jeff Dorsch - 15 Aug, 2018 - Comments: 2

Over the years, the semiconductor industry has witnessed a parade of packaging innovations, such as system-in-package, semiconductor embedded in substrate, and fan-out wafer-level packaging. Two interesting packaging innovations are now being used in the process of miniaturizing microchips and electronics. One is a new concept that combines two tried-and-true technologies. The other is a de... » read more

Return Of The Organic Interposer
By Ed Sperling - 06 Aug, 2018 - Comments: 2

Organic interposers are resurfacing as an option in advanced packaging, several years after they were first proposed as a means of reducing costs in 2.5D multi-die configurations. There are several reasons why there is a renewed interest in this technology: More companies are pushing up against the limits of Moore's Law, where the cost of continuing to shrinking features is exorbitant. ... » read more

Bridges Vs. Interposers
By Mark LaPedus - 12 Jul, 2018 - Comments: 4

The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

Complexity, Reliability And Cost
By Ed Sperling - 14 Jun, 2018 - Comments: 0

Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

Fan-Out Wars Begin
By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Warp Speed Ahead
By Ed Sperling - 11 Jan, 2018 - Comments: 3

The computing world is on a tear, but not just in one direction. While battery-powered applications are focused on extending the time between charges or battery replacements, there is a whole separate and growing market for massive improvements in speed. Ultimately, this is where quantum computing will play a role, probably sometime in the late 2020/early 2030 timeframe, according to multipl... » read more

Advanced Packaging Still Not So Simple
By Ed Sperling - 08 Jan, 2018 - Comments: 1

The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

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