tag: through-silicon vias

Fan-Out Wars Begin
By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Warp Speed Ahead
By Ed Sperling - 11 Jan, 2018 - Comments: 3

The computing world is on a tear, but not just in one direction. While battery-powered applications are focused on extending the time between charges or battery replacements, there is a whole separate and growing market for massive improvements in speed. Ultimately, this is where quantum computing will play a role, probably sometime in the late 2020/early 2030 timeframe, according to multipl... » read more

Advanced Packaging Still Not So Simple
By Ed Sperling - 08 Jan, 2018 - Comments: 1

The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

Advanced Packaging Is Suddenly Very Cool
By Ed Sperling - 11 Dec, 2017 - Comments: 2

The hottest chip markets today—automotive AI for autonomous and heavily assisted driving, machine learning, virtual and augmented reality—all are beginning to look at advanced packaging as the best path forward for improving performance and reducing power. Over the past four years, which is when 2.5D and fan-out wafer-level packaging first really began garnering interest, these and othe... » read more

Advanced Packaging Picks Up Steam
By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology. One of the big benefits of [getkc id="199" kc_name="SiP"] is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may ... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

What’s Next In Scaling, Stacking
By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

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