Advanced Packaging Is Suddenly Very Cool

In spite of the initial reasons for this technology, it is now viewed as the best way to handle large amounts of data at blazing speeds.


The hottest chip markets today—automotive AI for autonomous and heavily assisted driving, machine learning, virtual and augmented reality—all are beginning to look at advanced packaging as the best path forward for improving performance and reducing power.

Over the past four years, which is when 2.5D and fan-out wafer-level packaging first really began garnering interest, these and other advanced packaging options were seen as the least-cost alternative to scaling and the fastest way to bring chips to market. As it turns out, neither of those assumptions has proven true yet, and it’s not clear when they actually will.

While there is a move by DARPA to get an ecosystem of chiplet providers, and companies such as Marvell have created an internal architecture to more quickly assemble chips from pre-characterized IP, most of the interest in this market is about raw speed. Hundreds or thousands of through-silicon vias can move large quantities of data much faster than skinny wires, either in silicon or other types of interposers. The same is true for scaled-down bridges, such as Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) and Samsung’s proposed redistribution-layer (RDL) bridge.

Ironically, the reason that companies first began focusing on advanced packaging was that it was an alternative to shrinking, particularly for analog IP such as serializer/deserializer IP, which is basically a clever way of circumventing a limited number of pins on a chip to improve I/O. Analog IP doesn’t scale, so it seems obvious that the best approach is to leave it at the process node at which it has been developed, tested and proven, and simply add in whatever digital logic is needed at whatever node is best for a particular application.

That kind of granularity is still essential in advanced packaging, but the emphasis is less about third-party IP and the cost and time required to bring devices to market than the raw horsepower needed to move increasingly large quantities of data. It’s a classic plumbing problem. You can only jam so much stuff through a narrow pipe, regardless of whether it’s liquid or electrons. But as wires get skinnier and the dielectric material used to insulate them is thinned down to single digits of atoms, the heat generated by pushing more electrons through those wires over long distances—from one side of a chip to another—begins to climb. That produces all sorts of nasty effects, including electromigration, noise and performance and signal degradation.

There are ways to solve thermal issues. Power management schemes can be implemented so that whenever something gets too hot, circuits either shut down or signals are load balanced onto another circuit. But this is a lot of work. It makes verification more time consuming and raises more questions about system interactions, which can affect reliability. And it really doesn’t solve the problem of pushing large quantities of data back and forth through these extremely narrow-gauge wires.

This is where advanced packaging is beginning to win the most attention—semi-custom or completely custom designs with massive throughput for processing larger quantities of data more quickly. This resonates with the giant cloud providers, as well as the companies driving artificial intelligence for autonomous vehicles. It also works well in smart phones, where Apple is now marketing its latest phones as having two hours more battery life and faster processors. And it has been used in high-speed networking applications for at least the past couple years for exactly the same reasons.

In all of these cases, cost is a tertiary concern. These are largely price insensitive markets. But they also are the hottest technology markets today, and they almost certainly will elevate advanced packaging design to a level it has never achieved in the past. In effect, advanced packaging has arrived—but almost in spite of the rationale that created the initial interest in this technology.


Dev Gupta says:

” … It ( Adv. Packaging ) also works well in smart phones, where Apple is now marketing its latest phones as having two hours more battery life and faster processors… ”

How much of that improvement is really due to the use of new Packages ( e,g the FO WLP in which the A10 & now the A11 are packaged by their Foundry ) or denser PCBs ( called SLBs, in the X ) rather than the devices themselves ?

Losses in Package or Board interconnects happen due to parasitics and higher frequency / clock rates ( for a given Bandwidth both can be reduced drastically by TSVs which is why they are getting popular for HPC in spite of their cost ). But not much difference re: parasitics between the A9 that used the FC PoP and now the A10,11 using the thinner FO WLP.

William Travinha says:

The advance of 2.5D and 3D packaging will pose a big challenge to IC chip testing. We don’t have a standard for test access on MCM

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