tag: timing

Timing Challenges In The Age Of AI Hardware
By Quiyang Wu - 25 Feb, 2021 - Comments: 0

In recent years, we have seen a clear market trend towards dedicated integrated circuits (ASICs) that are much more efficient in performance and energy consumption than traditional general-purpose computers for processing AI workloads. These AI accelerators harden deep learning algorithm kernels into circuits, enable higher data ingestion bandwidth with local memory, and perform massively paral... » read more

Taming Non-Predictable Systems
By Brian Bailey - 28 Jan, 2021 - Comments: 0

How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

The Challenge Of Balancing Performance And Accuracy For Advanced Node Timing Signoff
By Rahul Deokar - 10 Nov, 2020 - Comments: 0

As process nodes shrink, complexity, cost and overall risk expand. Process variability that once was once acceptable now becomes a critical item as operating voltage decreases. Simply adding design margin makes the chip non-competitive. Physical effects that were once ignored now become critical as well. The impact of interconnect can no longer be modeled based on simple circuit topology. Layou... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

3 Types Of AI Hardware
By Ed Sperling - 20 Jul, 2020 - Comments: 1

As AI chips become more pervasive, three primary approaches are moving to the forefront. Bradley Geden, director of product marketing at Synopsys, looks at how to take advantage of repeatability, what the different flavors look like, the difference between flat and hierarchical design, and what impact black-box arrays have on programmability. » read more

Navigating Timing Margins Like Waze
By Noam Brousard - 13 Jul, 2020 - Comments: 0

Remember the pre-smartphone days, before navigation apps had our backs? Thanks to a lack of real-time visibility, ‘arriving early’ was the go-to strategy to avoid arriving late. Factor in too much ‘holdup time’ and you’d arrive a little too early. There’s nothing worse than nervously burning off an excess 30 minutes over a coffee you really didn’t need. Today you wouldn’t ... » read more

Timing Closure At 7/5nm
By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Timing Library LVF Validation For Production Design Flows
By WeiLii Tan - 27 Feb, 2020 - Comments: 3

Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Where Timing And Voltage Intersect
By Ed Sperling - 14 Feb, 2020 - Comments: 0

João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

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