tag: timing

Timing Is Of The Essence
By Ansys - 14 Mar, 2019 - Comments: 0

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

MISing In Signoff
By Jim McCanny - 31 Jan, 2019 - Comments: 0

Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

Why Chips Die
By Brian Bailey - 12 Nov, 2018 - Comments: 4

Semiconductor devices contain hundreds of millions of transistors operating at extreme temperatures and in hostile environments, so it should come as no surprise that many of these devices fail to operate as expected or have a finite lifetime. Some devices never make it out of the lab and many others die in the fab. It is hoped that most devices released into products will survive until they be... » read more

Carmakers To Chipmakers: Where’s The Data?
By Ed Sperling And Susan Rambo - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Achieving eFPGA Timing Closure In An ASIC
By Alok Sanghavi - 04 Oct, 2018 - Comments: 0

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems Engineering, discussed at the Design Automation Conference in June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA, such as Achronix’s Speedcore IP,... » read more

Will FPGAs Work As Expected?
By Ed Sperling - 27 Jul, 2018 - Comments: 1

OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs. https://youtu.be/RFlP2Z_-Yqs » read more

“Good Enough For Government Work?” Not Anymore.
By Ruben Molina - 26 Jul, 2018 - Comments: 0

When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as 40 years. To get an idea of how many people I’m talking about, there was a retirement party for at least 3 or 4 people every week just in our division. You can imagine tha... » read more

Aging Effects
By Ed Sperling - 17 Jul, 2018 - Comments: 0

Tech Talk: Fraunhofer EAS' group manager for quality and reliability, Andre Lange, talks about how to model aging effects and why the problems are becoming more difficult at advanced nodes. https://youtu.be/XHWww2PE7aY » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

The Week In Review: Design
By Jesse Allen - 22 Jun, 2018 - Comments: 0

Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

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