Chip Industry Technical Paper Roundup: Sept. 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=354 /] More ReadingTechnical Paper Library home » read more

Scalable Chiplet System for LLM Training, Finetuning and Reduced DRAM Accesses (Tsinghua University)


A new technical paper titled "Hecaton: Training and Finetuning Large Language Models with Scalable Chiplet Systems" was published by researchers at Tsinghua University. Abstract "Large Language Models (LLMs) have achieved remarkable success in various fields, but their training and finetuning require massive computation and memory, necessitating parallelism which introduces heavy communicat... » read more

Reasons To Know IGZO


Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

Research Bits: April 23


Probabilistic computer prototype Researchers at Tohoku University and the University of California Santa Barbara created a prototype of a heterogeneous probabilistic computer that combines a CMOS circuit with a limited number of stochastic nanomagnets. It aims to improve the execution of probabilistic algorithms used to solve problems where uncertainty is inherent or where an exact solution... » read more

3D Integration Supports CIM Versatility And Accuracy


Compute-in-memory (CIM) is gaining attention due to its efficiency in limiting the movement of massive volumes of data, but it's not perfect. CIM modules can help reduce the cost of computation for AI workloads, and they can learn from the highly efficient approaches taken by biological brains. When it comes to versatility, scalability, and accuracy, however, significant tradeoffs are requir... » read more

Chip Industry Technical Paper Roundup: Jan. 16


New technical papers added to Semiconductor Engineering’s library this week. [table id=188 /] More ReadingTechnical Paper Library home » read more

The 40-Million-Core Sunway Supercomputer: 5 ExaFlop/s HPL-MxP Benchmark With Linear Scalability


A technical paper titled “5 ExaFlop/s HPL-MxP Benchmark with Linear Scalability on the 40-Million-Core Sunway Supercomputer” was published by researchers at the National Research Center of Parallel Computer Engineering and Technology and Tsinghua University. Abstract: "HPL-MxP is an emerging high performance benchmark used to measure the mixed-precision computing capability of leading sup... » read more

Chip Industry Technical Paper Roundup: Dec 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

Hardware-Based Methodology To Protect AI Accelerators


A technical paper titled “A Unified Hardware-based Threat Detector for AI Accelerators” was published by researchers at Nanyang Technological University and Tsinghua University. Abstract: "The proliferation of AI technology gives rise to a variety of security threats, which significantly compromise the confidentiality and integrity of AI models and applications. Existing software-based so... » read more

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