Multi-model inference on chiplets; NIST chip standards; SLAM for autonomous driving; FTJ memristors for IMC accelerators; reconfigurable Si FETs; Sunway supercomputer; gallium oxide FETs; multi-level memory in quantum dots.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets | University of California Irvine |
| Semiconductors and Microelectronics Standards, Report of the Semiconductors and Microelectronics Working Group | NIST |
| Simultaneous Localization and Mapping (SLAM) for Synthetic Aperture Radar (SAR) Processing in the Field of Autonomous Driving | Ulm University |
| Ferroelectric Tunnel Junction Memristors for In-Memory Computing Accelerators | Lund University |
| Reconfigurable Si Field-Effect Transistors With Symmetric On-States Enabling Adaptive Complementary and Combinational Logic | TU Vienna and Swiss Federal Laboratories for Materials Science and Technology |
| 5 ExaFlop/s HPL-MxP Benchmark with Linear Scalability on the 40-Million-Core Sunway Supercomputer | National Research Center of Parallel Computer Engineering and Technology and Tsinghua University |
| Progress in Gallium Oxide Field-Effect Transistors for High-Power and RF Applications | George Mason University and NIST |
| Probing Optical Multi-Level Memory Effects in Single Core–Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters | KIST, DGIST, UST (Korea); National Institute for Materials Science (Japan) |
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