Thermal Challenges In Advanced Packaging


CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Week In Review: Manufacturing, Test


Chipmakers For some time, Intel has experienced supply constraints and shortages for its 14nm chip products. Apparently, the company is still having issues with both 14nm and 10nm. “Despite our best efforts, we have not yet resolved this challenge,” according to a statement from Michelle Johnston Holthaus, executive vice president and general manager of the Sales, Marketing and Communicati... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Different Ways To Improve Chip Reliability


A push toward greater reliability in safety- and mission-critical applications is prompting some innovative approaches in semiconductor design, manufacturing, and post-production analysis of chip behavior. While quality over time has come under intensive scrutiny in automotive, where German carmakers require chips to last 18 years with zero defects, it isn't the only market demanding extende... » read more

Leveraging Data In Chipmaking


John Kibarian, president and CEO of PDF Solutions, sat down with Semiconductor Engineering to talk about the impact of data analytics on everything from yield and reliability to the inner structure of organizations, how the cloud and edge will work together, and where the big threats are in the future. SE: When did you recognize that data would be so critical to hardware design and manufact... » read more

Week In Review: Manufacturing, Test


Chipmakers The IC industry once had several leading-edge vendors that invested and built new fabs. But over time, the field has narrowed due to soaring costs and a dwindling customer base. In 1994, the share of semiconductor industry capital spending held by the top five companies was 25%, according to IC Insights. This meant that a number of companies invested and built new fabs during the... » read more

Week In Review: Manufacturing, Test


Chipmakers China has created a new $29 billion fund to help advance its semiconductor sector, according to reports from Bloomberg and others. Here's another report. The The U.S. and China are in the midst of a trade war. This has prompted China to accelerate its efforts to become more self-sufficient in semiconductor design and production. This includes DRAMs as well as logic/foundry. -----... » read more

Migrating 3D Into The Mainstream


Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

Week in Review: IoT, Security, Autos


Products/Services Rambus reports completing the sale of its Payments and Ticketing businesses to Visa for $75 million in cash. “With 30 years of experience pushing the envelope in semiconductor design, we look toward a future of continued innovation to carry on our mission of making data faster and safer,” Rambus President and CEO Luc Seraphin said in a statement. “Completing this transa... » read more

IP Management And Development At 5/3nm


The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

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