tag: TSMC

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Crossing The Chasm: Uniting SoC And Package Verification
By Tarek Ramadan - 06 Mar, 2017 - Comments: 0

Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

What Next For OSATs
By Mark LaPedus - 06 Mar, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IC-packaging and business trends with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering ([getentity id="22930" comment="ASE"]), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What’s the outlook for the IC industry in 2017? Wu:... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 03 Mar, 2017 - Comments: 2

SPIE news At this week’s SPIE Advanced Lithography conference, the industry paid close attention to the progress of extreme ultraviolet (EUV) lithography. Here’s the general report card: EUV is making noticeable progress, but there are still some challenges ahead, such as the power source, resists and pellicles. Several issues need to be resolved before chipmakers can put EUV into mass... » read more

Semiconductor CapEx To Increase 4.3% In 2017
By Adrienne Downey - 20 Feb, 2017 - Comments: 0

Semiconductor capital expenditures are an important bellwether for the industry. Based on preliminary findings, Semico Research predicts 2017’s total will increase 4.3% to $69.7 billion, a record high, and a slightly larger increase than in 2016. Semico tracks more than 80 companies for CapEx and R&D spending, although many of those companies have merged, have been acquired, or gone ba... » read more

China Moves To Top Spot In Fab Equipment Spending
By Clark Tseng - 16 Feb, 2017 - Comments: 0

By Clark Tseng, Dan Tracy & Gavin Wang of SEMI With 20, and possibly more, new fab projects underway or announced in China since 2016, spending on fab equipment will surge to $10 billion or more, annually, by 2018 and to even higher levels in the following two years. As a result, China is projected to be the top spending region for fab equipment in 2019 and 2020. Robert Maire, of Semicon... » read more

The Week In Review: Design
By Jesse Allen - 10 Feb, 2017 - Comments: 0

IP Rambus unveiled High Bandwidth Memory (HBM) Gen2 PHY developed for GlobalFoundries' FX-14 ASIC platform. The PHY, targeted at networking and data center applications, is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, for a total bandwidth of 256 GB/s. Omnitek launched a number of new FPGA-based video IPs, including HDMI2.0 Tx and Rx, ... » read more

OSAT Biz: Growth And Challenges
By Mark LaPedus - 08 Feb, 2017 - Comments: 0

Amid a challenging business environment, the outsourced semiconductor assembly and test (OSAT) industry is projected to see steady to strong growth in a number of packaging segments this year. Right now, the [getkc id="83" kc_name="OSATs"]—which provide third-party IC-packaging and test services—are seeing brisk demand for both legacy and advanced chip packages. In addition, IDMs continu... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Changing Direction In Chip Design
By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

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