The Week In Review: Design

Memory design and verification; process variation; IP for 5G; auto IP.


Cadence unveiled an integrated memory design and verification tool, with environments for bitcell design, array and complier verification, and memory characterization. It utilizes existing simulation databases for multi-corner and Monte Carlo analysis, which the company says can lead to a 2X runtime improvement.

Solido Design Automation uncorked PVTMC Verifier, which uses machine learning to verify designs across the spectrum of process variation and operating conditions. It takes into account interactions between statistical variation and PVTs to identify worst-case conditions, and according to the company is more than 100x faster than the equivalent brute force verification.

Synopsys released the latest version of its optical design software, adding faster modulation transfer function (MTF) optimization, better design visualization for small, highly aspheric lenses such as those found in smartphones, and enhanced materials databases.

Imec announced two low-power IP blocks for future 5G applications. The first is a compact successive approximation analog-to-digital converter (SAR ADC), designed for consumer electronics operating in the below-6GHz frequency bands (4G/5G). The second is a 60GHz front-end with RF phase shifting and on-chip transmit-receive switching, targeting 5G fixed wireless access and small cell backhaul applications.

Cadence launched a portfolio of automotive-focused IP for TSMC 16nm FinFET Compact process. It includes IP for infotainment and ADAS systems, including 4266-speed grade LPDDR4/4X DDR PHY and controllers and PCIe4/3 PHY and controllers, as well as subsystems supporting MIPI D-PHYSM, USB3.1/USB2.0, DisplayPort, Octal SPI/QSPI, UFS and Gigabit Ethernet with TSN. The IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range and is ASIL-B ready and ASIL-C/D capable.

Kilopass won a deal with Northrop Grumman, which used ultra-low power Kilopass OTP NVM for encryption key storage in a 0.01-mm2 advanced silicon processor. The processor is part of a DARPA project to prevent counterfeit devices from entering the DoD supply chain.

Samsung SARC selected Synopsys’ verification platform as the primary solution for its high-performance, low-power mobile CPU, GPU and system IP designs.

Flex Logix joined the TSMC IP Alliance Program. The company’s eFPGA IP and software tools are available for TSMC 16FFC/FF+, TSMC 28HPM/HPC and TSMC 40ULP/LP.

UltraSoC’s embedded analytics IP will be made available through SiFive’s DesignShare ecosystem to provide debug and trace technology for SiFive’s RISC-V SoCs.

Menta eFPGAs are now available with embedded SureCore low-power SRAM IP. Targeted for mobile, base stations and IoT products, the eFPGA core IP includes 800 LUT6 equivalent, six 18bit MAC and 6Kb of sureCore single port SRAM in the TSMC 28HPC+ technology node running at 0.9V. It can be customized with various amount of LUTs, DSPs and SRAM.

Ty Garibay joined ArterisIP as the company’s new CTO. Garibay was VP of IC Engineering for Altera and, later, led Intel’s FPGA IC design. He previously managed ARM’s Austin Design Center and held positions at TI, Motorola, Cyrix, SGI, and Alchemy Semiconductor.

Srikanth Rengarajan joined Austemper Design Systems as VP of products and business development. A former associate director at Broadcom, Rengarajan previously held positions at AMD and Marvell.

TSMC OIP Ecosystem Forum: Sept. 13 in Santa Clara, CA. Focused on TSMC’s design ecosystem companies, discussions include advanced node design challenges, design enablement platforms, and best practices.

D&R IP-SoC Days: Sept. 14 in Shanghai, China. The event will host sessions ranging from eFPGAs, IoT, design methodologies, and interface IP.

DVCon India: Sept. 14-15 in Bangalore, India. Focused on the design and verification of IP, SoCs and electronic systems, this year features keynotes on the changing requirements for verification, deep learning, autonomous cars, and the next wave of verification.

IR4 (Fourth Industrial Revolution): The Cognitive Era: Sept. 20, 6-8:30pm at San Jose State University, San Jose, CA. Jim Hogan will discuss cognitive science, how it brings together methods and discoveries from neuroscience, psychology, linguistics, philosophy and data/computer science, and how people, animals or computers think, act and learn.

ARC Processor Summit: Sept. 26 in Santa Clara, CA. Opening with a keynote by Jeff Bier of the Embedded Vision Alliance and BDTI on how AI and machine learning are transforming electronic products, the day features concurrent tracks dedicated to hardware, software, and embedded vision.

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