tag: TSVs

Thermal Floorplanning For Chips
By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Shortages, Challenges Engulf Packaging Supply Chain
By Mark LaPedus - 18 Feb, 2021 - Comments: 0

A surge in demand for chips is impacting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, key components, and equipment. Spot shortages in packaging surfaced in late 2020 and have since spread to other sectors. There are now a variety of choke points in the supply chain. Wirebond and flip-chip capacity will remain tight throughout 2021... » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

Defect Challenges Grow For IC Packaging
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages. While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools. For years, p... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

EDA On Board With New Package Options
By Ann Mutschler - 22 Jul, 2020 - Comments: 2

A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

The Next Advanced Packages
By Mark LaPedus - 18 Jun, 2020 - Comments: 4

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

SEMI 3D1 – Terminology For Through Silicon via Geometrical Metrology
By SEMI - 17 Jun, 2020 - Comments: 0

Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). Click here to read more, fee for access. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy